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參數(shù)資料
| 型號： | XRD9818ACGTR |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 16B CCD/CIS SIG PROC 28TSSOP |
| 產品變化通告： | Leaded UART, V&I Obsolescence 11/Apr/2011 |
| 標準包裝： | 1,500 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 325mW |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
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XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
13
* Power-on default lt value
PD - Power Down. Does not affect the internal register settings but does power down the entire part
excluding the serial interface. There will be some power up settling time required to
reestablish the ADC reference, CAPP and CAPN, voltages.
OE - Output Enable. Tristate control for the output data bus.
LPOL - LCLMP input polarity select. (Noninverting pol active high, inverted pol active low)
ADCPOL - ADCLK polarity select. (Noninverting pol begins high, inverted pol begins low)
BPOL - BSAMP polarity select. (Noninverting pol active high, inverted pol active low)
VPOL - VSAMP polarity select. (Noninverting pol active high, inverted pol active low)
3.4
BSAMP Delay Register
The BSAMP Delay register controls the internal delays added to the leading and the trailing edges of the
BSAMP timing signal. The width and position of the BSAMP pulse can be adjusted through the leading and
trailing edge delay settings. This is useful to match the sampling requirements of the incoming CCD waveform.
* Power-on default value
BL[4:0] - Sets the amount of delay added to the leading edge of BSAMP.
BT[4:0] - Sets the amount of delay added to the trailing edge of BSAMP.
MODE 2 REGISTER SETTINGS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PD
OE
N/A
LPOL
ADCPOL
BPOL
VPOL
0*
→ Normal Opera-
tion
1
→ PWR Down
0*
→ Normal Oper-
ation
1
→ Data bus
tri-stated
Not
used
Not
used
Not
used
Not
used
0*
→ Non-
Inverted
1
→ Inverted
0*
→ Non-
Inverted
1
→ Inverted
0*
→ Non-
Inverted
1
→ Inverted
0*
→ Non-
Inverted
1
→ Inverted
BSAMP DELAY REGISTER SETTINGS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BL[4]
BL[3]
BL[2]
BL[1]
BL[0]
BT[4]
BT[3]
BT[2]
BT[1]
BT[0]
BSAMP Leading edge delay
00000*
→ 0ns
00001
→ 1ns
…
11110
→ 30ns
11111
→ 31ns
BSAMP Trailing edge delay
00000*
→ 0ns
00001
→ 1ns
…
11110
→ 30ns
11111
→ 31ns
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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