Rev. 1.00 VSAMP Timing This allows the user to select one of two VSAMP timing controls. Timing Option #2 allows the rising ed" />
參數(shù)資料
型號: XRD9816BCV-F
廠商: Exar Corporation
文件頁數(shù): 8/53頁
文件大?。?/td> 0K
描述: IC 16BIT CCD/CIS SIG PROC 48TQFP
標(biāo)準(zhǔn)包裝: 250
位數(shù): 16
通道數(shù): 3
電壓 - 電源,模擬: 4.5 V ~ 5.5 V
電壓 - 電源,數(shù)字: 3 V ~ 5.5 V
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
XRD9814B/9816B
16
Rev. 1.00
VSAMP Timing
This allows the user to select one of two VSAMP timing
controls. Timing Option #2 allows the rising edge of
VSAMP to occur approximately one-half ADCCLK
earlier than Option #1. This does not affect internal
timing and is provided only to allow additional flexibility
in the external timing control. Timing Option #2 is
available only in the 3-channel mode of operation (See
timing diagrams Figure 3 and Figure 4).
Configuration Register #2
The bit assignment and definition for this register is
detailed in the Configuration Register #2 Definition
Table. A diagnostic read-back mode allows gain,
offset and configuration data to be output as the 8 or 10
MSBs on the digital output bus depending on the
selection of OUTSEL (see Reading Register Data
session for details). Additional bits are used to enable
a low-power stand-by state and manufacturing test
mode.
Digital Reset
Setting this bit to one resets all registers to all zeros.
Test Mode
This is a reserved bit for testing and must be set to 0
in all writes to Configuration Register #2.
Stand-By Mode
Setting this bit to one forces the circuit into a low-power
standby mode. Configuration, offset and gain registers
remain unchanged in stand-by mode. Pull OEB High
to set DB<15:0> to high impedance during stand-by
mode.
Read Back Mode
This is a special diagnostic mode which can aid in the
debugging of new system designs. Setting this bit to 1
allows all configuration, gain and offset register con-
tents to be output on the data output bus (explained
below).
Reading Register Data
In order to enter read-back mode, set configuration
register #2, PB0 to 1. Follow the write timing in Figures
17 and 18.
In order to read a specific register, shift in 3-bits of
register address data (MSB first), followed by 10
dummy data bits. In the case of reading back configu-
ration register #2, PB0 has to stay 1 and cannot be a
dummy.
In order to exit read-back mode perform a write to
configuration register 2, PB0=0.
(OUTSEL = 0) In read-back mode the A/D output is
bypassed and internal register data is output to the 10
most significant bits of the data output bus. The
remaining LSB bits should be ignored. Register data
will be valid after the load pin goes high.
(OUTSEL = 1) In nibble mode, the output bus is limited
to 8-bits. Therefore, in read-back mode, the 8 MSBs
are valid when ADCCLK is high, and the 2 LSBs are
valid when ADCCLK is low. Configuring and exiting the
read-back mode is done in the same manner of
OUTSEL = 0.
Important: The entire byte of register #2 is re-written when
exiting the readback mode. If any bits of configuration
register #2 were programmed prior to entering the read-
back mode, they must be re-programmed when exiting
read-back. See Figure 19 for read-back timing.
PGA Gain Settings
The gain for each color input is individually program-
mable from 1 to 10 in 1024 linear steps.
001 XXXXXXXXX1
010 XXXXXXXXXX
Cfig2
Red Gain
011 XXXXXXXXXX
Grn Gain
100 XXXXXXXXXX
Blu Gain
101 XXXXXXXXXX
Red Offset
110 XXXXXXXXXX
111 XXXXXXXXXX
001 XXXXXXXXXX
Cfig1
Blu Offset
Grn Offset
Address
Data
Register
Read-Back Registers and Address
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