- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3766 > XR88C681CP/40-F (Exar Corporation)IC UART CMOS DUAL 40PDIP PDF資料下載
參數(shù)資料
| 型號： | XR88C681CP/40-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 77/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART CMOS DUAL 40PDIP |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 1 字節(jié)，3 字節(jié) |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 帶并行端口： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-PDIP |
| 包裝： | 管件 |
| 其它名稱： | 1016-1328-5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁當(dāng)前第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁
XR88C681
77
Rev. 2.11
MR2n[3:0] - Stop Bit Length
This bit field programs the duration of the stop bits
appended to each transmitted character.
Stop bit
duration of 9/16 to 1 bit time and 1 9/16 to 2 bit times, in
increments of 1/16 bits can be programmed for character
lengths of 6, 7 and 8 bits. For a 5 bit character, the stop bit
duration can be programmed from 1-1/16 to 2 bit times.
If an external 1x clock is programmed for the transmitter
clock (TXCn), MR2n[3] = 0 selects a stop bit duration of
one bit time and MR2n[3] = 1 selects a duration of two bit
times for transmission.
The receiver only checks for mark condition at the center
of the first stop bit (that is, one bit time after the last data or
parity bit is sampled) regardless of the programmed
transmitted stop bit length. If the receiver does not sample
a “mark” a “Frame Error” (FE) is flagged in the Status
Register.
G.4 Status Register, SRn
The Status Register provides the user with status on the
RHR and THR (Receiver and Transmitter FIFOs,
respectively); and serves to provide the CPU with a
measure of the quality of the reception of data by the
receiver. FIFO Status indicators are useful in polled
systems and allows the CPU to check and see if the
Transmitter is empty and/or is ready for data from the
CPU. The FIFO Status indicators also indicate whether or
not the RHR has a character, which is waiting to be read
by the CPU, or is full and incapable of receiving any more
characters without an overrun. The Transmitter and
Receiver FIFO status indicators are located in the lower
nibble of the Status Register.
The upper nibble of the Status Register alerts the user of
any data reception errors. The bit-format of the Status
Register and a discussion of each bit follows:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Received
Break
Framing Error
Parity Error
Overrun
Error
TXEMT
TXRDY
FFULL
RXRDY
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
Table 28. Status Register - SRA, SRB
SRn[7] Received Break
This bit indicates that an all zero character of the
programmed character length was received without a
stop bit. Only a single FIFO position is occupied when a
break is received. Additional transfers into the FIFO are
inhibited until the RXD line returns to the marking state for
at least half a bit time. This is defined as two successive
edges of the internal or external 1x clock.
When this bit is set, the channel’s “CHANGE IN BREAK
STATUS” bit in the ISR is set. The bit in the ISR is also set
when the end of the break condition, as defined above, is
detected.
The chip’s break detect logic can detect breaks that begin
in the middle of a character. However, the break must
persist until the end of the next character time in order for it
to be detected.
If the Error Mode, of the channel, has been set to
“Character” Mode, this bit only applies to the Character at
the top of the RHR. This bit will be cleared if the RXDn
input is brought to a logic “high” level, in the next
character.
If the “Error” Mode has been set to “Block” mode, then this
bit, once set will remain asserted until the “RESET
ERROR STATUS” command has been invoked (please
see
Table 3). Please note that if the Error Mode is “Block”
this bit, in the Status Register will remain set, for all
subsequent characters, independent of the condition of
these received characters, until the “RESET ERROR
STATUS” command has been invoked.
SRn[6] Framing Error
Following reception of the character bits, and any
associated parity bit, the Receiver will check for a “mark”
condition one bit-time following the last data or parity bit.
This “mark” condition is the STOP bit. If the Receiver
does not detect a “mark” at this time, the bit is toggled
“high” flagging the occurrence of a Frame Error (FE).
If the Error Mode has been set to “Character” Mode, this
bit only applies to the Character at the top of the RHR. If
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT89C51RB2-RLRIM | IC MCU FLASH 8051 16K 5V 44-VQFP |
| XR16V2550IM-F | IC UART FIFO 16B 48TQFP |
| MAX7311AWG+T | IC I/O EXPANDER I2C 16B 24SOIC |
| XR16L2750CM-F | IC UART FIFO 64B DUAL 48TQFP |
| XR20M1172IL32-F | IC UART FIFO I2C/SPI 64B 32QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR88C681J | 制造商:Exar Corporation 功能描述: |
| XR88C681J-F | 功能描述:UART 接口集成電路 0.5V-2V UART temp -45 to 85C RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR88C681JTR-F | 功能描述:UART 接口集成電路 Dual Channel UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR88C681MN-S0968 | 制造商:Exar Corporation 功能描述: |
| XR88C681N/40 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CMOS DUAL CHANNEL UART (DUART) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。