TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B DLM, DLL DLM = 0x00 and DLL " />
參數(shù)資料
型號： XR68M752IB-0A-EVB
廠商： Exar Corporation
文件頁數(shù)： 33/54頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR 68M752 49BGA
標(biāo)準(zhǔn)包裝： 1
系列： *
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B
DLM, DLL
DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up.
They do not reset when the Reset Pin is asserted.
DLD
Bits 7-0 = 0x00
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x1D
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
TCR
Bits 7-0 = 0x0F
TLR
Bits 7-0 = 0x00
FIFO Rdy
Bits 7-0 = 0x03
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
XON2
Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
XOFF1
Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
XOFF2
Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
I/O SIGNALS
TX
HIGH
OP2#
HIGH
RTS#
HIGH
DTR#
HIGH
RXRDY#
HIGH
TXRDY#
LOW
INT
Three-State Condition
XR16M752/XR68M752
39
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REGISTERS
RESET STATE
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