REV. 1.3.0 FLOW_CONTROL[2:0]: Flow control mode select FLOW_CONTROL[3]: Half-Duplex Mode
參數(shù)資料
型號(hào)： XR21V1412IL32-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO USB DUAL 32QFN
產(chǎn)品培訓(xùn)模塊： UART Product Overview
XR21V141x Full-Speed USB UART Family
特色產(chǎn)品： XR21V141x Full-Speed USB UART
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)，384 字節(jié)
規(guī)程： USB 2.0
電源電壓： 2.97 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 托盤
配用： 1016-1301-ND - EVAL BOARD FOR XR21V1412IL
其它名稱： 1016-1302
XR21V1412
22
2-CH FULL-SPEED USB UART
REV. 1.3.0
FLOW_CONTROL[2:0]: Flow control mode select
FLOW_CONTROL[3]: Half-Duplex Mode
Logic 0 = Normal (full-duplex) mode. The UART can transmit and receive data at the same time.
Logic 1 = Half-duplex Mode. In half-duplex mode, any data on the RX pin is ignored when the UART is
transmitting data.
FLOW_CONTROL[7:4]: Reserved
These bits are reserved and should remain ’0’.
3.3.7
XON_CHAR, XOFF_CHAR Register Descriptions (Read/Write)
The XON_CHAR and XOFF_CHAR registers store the XON and XOFF characters, respectively, that are used
in the Automatic Software Flow control. If the V1412 is configured in multidrop mode, the XON_CHAR and
XOFF_CHAR registers are instead used for address matching.
XON_CHAR[7:0]: XON Character
In Automatic Software Flow control mode, the UART will resume data transmission when the XON character
has been received.
For behavior in the Address Match mode, see “Section 1.5.9, Multidrop Mode with address matching” on
page 12.
XOFF_CHAR[7:0]: XOFF Character
In Automatic Software Flow control mode, the UART will suspend data transmission when the XOFF character
has been received.
For behavior in the Address Match mode, see “Section 1.5.9, Multidrop Mode with address matching” on
page 12.
3.3.8
LOOPBACK_CTL Register Descriptions (Read/Write)
LOOPBACK_CTL[0]: Channel
Logic 0 = UART Channel A
Logic 1 = UART Channel B
LOOPBACK_CTL[1]: Reserved
This bit is reserved and should remain ’0’.
TABLE 13: FLOW CONTROL MODE SELECTION
MODE
BIT-2 BIT-1 BIT-0
MODE DESCRIPTION
0
No flow control, no address matching.
1
0
1
HW flow control enabled. Auto RTS/CTS or DTR/DSR must be selected by
GPIO_MODE.
2
0
1
0
SW flow control enabled
3
0
1
Multidrop mode - RX only after address match, TX independent. (Typically
used with GPIO_MODE 3)
4
1
0
Multidrop mode - RX / TX only after address match. (Typically used with
GPIO_MODE 4)
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