REV. 1.0.4 1.4 Device Configuration Registers The Device Configuration Regist" />
參數(shù)資料
型號： XR17V358IB176-F
廠商： Exar Corporation
文件頁數(shù)： 10/68頁
文件大?。?/td> 0K
描述： IC UART PCIE OCTAL 176FPBGA
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
UART Product Overview
標(biāo)準(zhǔn)包裝： 160
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 256 字節(jié)
規(guī)程： RS485
電源電壓： 1.2V，3.3V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 176-LFBGA
供應(yīng)商設(shè)備封裝： 176-FPBGA（13x13）
包裝： 托盤
配用： 1016-1296-ND - EVAL BOARD FOR XR17V358-E8
1016-1295-ND - EVAL BOARD FOR XR17V358-E4
1016-1293-ND - EVAL BOARD FOR XR17V358
其它名稱： 1016-1294
XR17V358
18
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
1.4
Device Configuration Registers
The Device Configuration Registers provide easy programming of general operating parameters to the V358
and for monitoring the status of various functions. These registers control or report on all 8 channel UARTs
functions that include interrupt control and status, 16-bit general purpose timer control and status, multipurpose
inputs/outputs control and status, sleep mode control, soft-reset control, and device identification and revision,
and others. Tables 5 and 6 below show these registers in BYTE and DWORD alignment. Each of these
registers is described in detail in the following paragraphs.
TABLE 5: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT
ADDRESS [A7:A0]
REGISTER
READ/WRITE COMMENT
RESET STATE
Ox080
INT0 [7:0]
Read-only Interrupt [7:0]
Bits [7:0] = 0x00
Ox081
INT1 [15:8]
Read-only
Bits [7:0] = 0x00
Ox082
INT2 [23:16]
Read-only
Bits [7:0] = 0x00
Ox083
INT3 [31:24]
Read-only
Bits [7:0] = 0x00
Ox084
TIMERCNTL
Read/Write Timer Control
Bits [7:0] = 0x00
Ox085
REGA
Reserved
Bits [7:0] = 0x00
Ox086
TIMERLSB
Read/Write Timer LSB
Bits [7:0]= 0x00
Ox087
TIMERMSB
Read/Write Timer MSB
Bits [7:0]= 0x00
Individual UART channels can only control the bit
pertaining to that channel in the registers at address
offset 0x088-0x08B.
Ox088
8XMODE
Read/Write
Bits [7:0] = 0x00
Ox089
4XMODE
Read/Write
Bits [7:0] = 0x00
Ox08A
RESET
Write-only Self clear bits after executing Reset
Bits [7:0] = 0x00
Ox08B
SLEEP
Read/Write Sleep mode
Bits [7:0]= 0x00
Ox08C
DREV
Read-only Device revision
Bits [7:0] = Current Rev.
Ox08D
DVID
Read-only Device identification
Bits [7:0] = 0x88
Ox08E
REGB
Read/Write EEPROM control
Bits [7:0] = 0x00
Ox08F
MPIOINT[7:0]
Read/Write MPIO[7:0] interrupt mask
Bits [7:0] = 0x00
Ox090
MPIOLVL[7:0]
Read/Write MPIO[7:0] level control
Bits [7:0] = 0x00
Ox091
MPIO3T[7:0]
Read/Write MPIO[7:0] output control
Bits [7:0] = 0x00
Ox092
MPIOINV[7:0]
Read/Write MPIO[7:0] input polarity select
Bits [7:0] = 0x00
Ox093
MPIOSEL[7:0]
Read/Write MPIO[7:0] select
Bits [7:0] = 0xFF
0x094
MPIOOD[7:0]
Read/Write MPIO[7:0] open-drain output control
Bits [7:0] = 0x00
Ox095
MPIOINT[15:8]
Read/Write MPIO[15:8] interrupt mask
Bits [15:8] = 0x00
Ox096
MPIOLVL[15:8]
Read/Write MPIO[15:8] level control
Bits [15:8] = 0x00
Ox097
MPIO3T[15:8]
Read/Write MPIO[15:8] output control
Bits [15:8] = 0x00
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