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參數(shù)資料
| 型號(hào)： | XR17V358IB-E4-EVB |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 3/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR17V358-E4 |
| 產(chǎn)品培訓(xùn)模塊： | PCIe UARTs UART Product Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，UART |
| 嵌入式： | 否 |
| 已用 IC / 零件： | XR17V358 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA |
| 其它名稱： | 1016-1295 |
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XR17V358
11
REV. 1.0.4
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
OFFSET
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX OR BINARY)
0x00
31:16
EWR
Device ID - No slave device on expansion interface
Device ID - XR17V358 slave device on expansion interface
Device ID - XR17V354 slave device on expansion interface
0x0358
0x8358
0x4358
15:0
EWR
Vendor ID (Exar) specified by PCISIG
0x13A8
0x04
31
30
RWC
Parity error detected. Cleared by writing a logic 1.
System error detected. Cleared by writing a logic 1.
0b
29:28
RO
Unused
00b
27
RO
Target Abort.
0b
26:25
RO
DEVSEL# timing.
00b
24
RO
Unemployments bus master error reporting bit
0b
23
RO
Fast back to back transactions are supported
0b
22
RO
Reserved Status bit
0b
21
RO
66MHz capable
0b
20
RO
Capabilities List
1b
19:16
RO
Reserved Status bits
0000b
15:11,
9,7, 5,
4, 3, 2
RO
Command bits (reserved)
0x0000
10
RWR
This bit disables the device from asserting INTx#. logic 1 = dis-
able assertion of INTx# and logic 0 = enables assertion of INTx#
0b
8
RWR
SERR# driver enable. logic 1=enable driver and 0=disable driver
0b
6
RWR
Parity error enable. logic 1=respond to parity error and 0=ignore
0b
1
RWR
Command controls a device’s response to mem space accesses:
0=disable mem space accesses, 1=enable mem space accesses
0b
0
RO
Device’s response to I/O space accesses is disabled.
(0 = disable I/O space accesses)
0b
0x08
31:8
EWR
Class Code (Default is ’Simple 550 Communication Controller’)
0x070002
7:0
RO
Revision ID (Exar device revision number)
Current Rev. value
0x0C
31:24
RO
BIST (Built-in Self Test)
0x00
23:16
RO
Header Type (a single function device with one BAR)
0x00
15:8
RO
Unimplemented Latency Timer (needed only for bus master)
0x00
7:0
RO
Unimplemented Cache Line Size
0x00
0x10
31:14
RWR
Memory Base Address Register (BAR0)
0x00000
13:0
RO
Claims an 16K address space for the memory mapped UARTs
including the UARTs on the expansion interface.
0x0000
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