REV. 1.0.4 3.2 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation" />
參數(shù)資料
型號: XR17V358IB-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 32/68頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR17V358
產(chǎn)品培訓模塊: PCIe UARTs
UART Product Overview
標準包裝: 1
主要目的: 接口,UART
嵌入式:
已用 IC / 零件: XR17V358
已供物品:
相關產(chǎn)品: 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA
其它名稱: 1016-1293
XR17V358
38
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
3.2
Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
Automatic hardware or RTS/DTR and CTS/DSR flow control is used to prevent data overrun to the local
receiver FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request remote unit to
suspend/restart data transmission while the CTS#/DSR# input pin is monitored to suspend/restart local
transmitter. The auto RTS/DTR and auto CTS/DSR flow control features are individually selected to fit specific
application requirement and enabled through EFR bit[7:6] and MCR bit [2] for either RTS/CTS or DTR/DSR
control signals. The auto RTS/DTR function must be started by asserting RTS/DTR# output pin (MCR bit [0] or
bit [1] to logic 1) after it is enabled. Figure 10 below explains how it works.
Two interrupts associated with RTS/DTR and CTS/DSR flow control have been added to give indication when
RTS/DTR# pin or CTS/DSR# pin is de-asserted during operation. The RTS/DTR and CTS/DSR interrupts must
be first enabled by EFR bit [4], and then enabled individually by IER bits [7:6], and chosen with MCR bit [2].
Automatic hardware flow control is selected by setting bits [7 (CTS): 6 (RTS)] of the EFR register to logic 1. If
CTS# pin transitions from LOW to HIGH indicating a flow control request, ISR bit [5] will be set to logic 1, (if
enabled via IER bit [7:6]), and the UART will suspend TX transmissions as soon as the stop bit of the character
in process is shifted out. Transmission is resumed after the CTS# input returns to LOW, indicating more data
may be sent.
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