REV. 1.0.2 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT PIN DESCRIPTIONS NAME
參數(shù)資料
型號： XR17V258IVTR-F
廠商： Exar Corporation
文件頁數(shù)： 23/69頁
文件大?。?/td> 0K
描述： IC UART PCI BUS OCTAL 144LQFP
標(biāo)準(zhǔn)包裝： 750
特點： *
通道數(shù)： 8
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V，5V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 帶卷 (TR)
XR17V258
3
REV. 1.0.2
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
PIN DESCRIPTIONS
NAME
PIN #
TYPE
DESCRIPTION
PCI LOCAL BUS INTERFACE
RST#
134
I
PCI bus reset input (active LOW). It resets the PCI local bus configuration
space registers, device configuration registers and UART channel registers to
the default condition.
CLK
135
I
PCI bus clock input of up to 66.67MHz.
AD31-AD25,
AD24,
AD23-AD16,
AD15-AD8,
AD7-AD0
138-144,
1,
6-13,
26-33,
37-44
IO
Address data lines [31:0] (bidirectional).
FRAME#
15
I
Bus transaction cycle frame (active LOW). It indicates the beginning and
duration of an access.
C/BE0#-
C/BE3#
36,25,14,2
I
Bus command/byte enable [3:0] (active LOW). This line is multiplexed for bus
command during the address phase and byte enables during the data phase.
IRDY#
16
I
Initiator ready (active LOW). During a write, it indicates that valid data is
present on data bus. During a read, it indicates the master is ready to accept
data.
TRDY#
17
O
Target ready (active LOW).
STOP#
21
O
Target request to stop current transaction (active LOW).
IDSEL
3
I
Initialization device select (active HIGH).
DEVSEL#
18
O
Device select to the XR17V258 (active LOW).
INTA#
133
OD
Device interrupt from XR17V258 (open drain, active LOW).
PME#
111
OD
Power Management Event signal. While in D3hot state, if the PME_Enable bit
in the Power Management Control/Status Register is set, the V258 asserts
the PME# upon receiving a new character or upon change of state of modem
inputs on any channel.
PAR
24
IO
Parity is even across AD[31:0] and C/BE[3:0]# (bidirectional, active HIGH).
PERR#
22
O
Data parity error indicator, except for special cycle transactions (active LOW).
Optional in bus target application.
SERR#
23
OD
System error indicator, Address parity or data parity during special cycle
transactions (open drain, active LOW). Optional in bus target application.
MODEM OR SERIAL I/O INTERFACE
TX0
125
O
UART channel 0 Transmit Data or infrared transmit data.
RX0
132
I
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted internally prior to
decoding by setting FCTR bit [4].
RTS0#
127
O
UART channel 0 Request to Send or general purpose output (active LOW).
CTS0#
131
I
UART channel 0 Clear to Send or general purpose input (active LOW).
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