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XR17C158
xr
5V PCI BUS OCTAL UART
REV. 1.4.3
64
REVISION HISTORY
DATE
REVISION
DESCRIPTION
March 2000
Rev. 1.0.1
Preliminary
March 2001
Rev. 1.0.2
Corrected patent number, front page; reference to DAN112; corrected CTS#, DSR#, RI#
and CD# in figure 11 internal loopback; shaded MCR bit-2 and EFR bit-4 in table 11; fixed
“(ISR bit=1)” in figure 12; clarified MCR bits 2 and 6; update 5V electrical characteristics
tables with Icc and Isleep current, and added 3.3V electrical characteristics tables
May 2001
Rev. 1.1.0
Deleted ICH and ICL from Electrical tables. Finalized and changed values in 3.3V Electri-
cal table. Corrected spelling. Changed data sheet from Preliminary to Final.
June 2001
Rev. 1.1.1
Corrected VIH (2.0 to 2.4V) in DC Electrical Characteristics Tables.
August 2001
Rev. 1.1.2
Clarified EECS, PERR# & SERR# hardware pin descriptions, MSR Register and Software
Flow Control Functions. Added Programming Examples to explain unloading receive data
using the Special Receive FIFO Data with Status.
December 2001
Rev. 1.1.3
Changed VIL max from 0.8 to 0.7V. Changed condition on ICC from CLK=50MHz to “
PCIClk=2MHz, EXT Clock=2Mhz”. Changed Condition on VOL from Iout=6mA to 4mA.
Changed Condition on VOH from Iout=-2mA to -1mA.
May 2003
Rev 1.2.0
Changed to single column format. Added uarttechsupport e-mail address to last page.
September 2003 Rev 1.3.0
Added Device Status to Ordering Information. Clarified RS485 description. Added
description for PCI Burst Read and PCI Burst Write. Added wake-up indicator to interrupt
source table.
May 2004
Rev 1.4.0
Clarified pin descriptions- changed from using logic 1 and logic 0 to HIGH (VCC) and LOW
(GND) for input and output pin descriptions. The XR17C158 is a 5V Only PCI Octal UART
(removed 3.3V electrical characteristics). For a 3.3V PCI Octal UART, please see the
XR17D158. The Device Revision Register (DREV) has been updated to 0x08 for devices
with top mark date code "H2 YYWW".
November 2004 Rev 1.4.1
The Device Revision Register (DREV) has been updated to 0x09 for devices with top
mark date code "I2 YYWW".
January 2005
Rev 1.4.2
The programming examples to unload data from the special RX FIFO + LSR data register
were updated to use a dummy write to DVID instead of a dummy read to DVID to prevent
the byte swapping in the devices with top mark date code of "GC YYWW" and older.
August 2005
Rev 1.4.3
Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP" to "LQFP" to
be consistent with JEDEC and Industry norms.