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參數(shù)資料
| 型號： | XR16V794IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 50/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 64B QUAD 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.25 V ~ 3.6 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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XR16V794
6
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.1
1.0
DESCRIPTION
The XR16V794 (794) integrates the functions of 4 enhanced 16550 UARTs, a general purpose 16-bit timer/
counter and an on-chip oscillator. The device configuration registers include a set of four consecutive interrupt
source registers that provides interrupt-status for all 4 UARTs, timer/counter and a sleep wake up indicator.
Each UART channel has its own 16550 UART compatible configuration register set for individual channel
control, status, and data transfer. Additionally, each UART channel has 64-byte of transmit and receive FIFOs,
automatic RTS/CTS or DTR/DSR hardware flow control with hysteresis control, automatic Xon/Xoff and special
character software flow control, programmable transmit and receive FIFO trigger levels, FIFO level counters,
infrared encoder and decoder (IrDA ver. 1.0), programmable baud rate generator with a prescaler of divide by
1 or 4, and data rate up to 8Mbps with 8X sampling clock or 4Mbps with 16X sampling clock. The XR16V794 is
a 2.25-3.6V device with 5 volt tolerant inputs (except XTAL1).
2.0
FUNCTIONAL DESCRIPTIONS
2.1
Device Reset
2.1.1
Hardware Reset
The RST# input resets the internal registers and the serial interface outputs in all 4 channels to their default
state (see Table 19). A LOW pulse of longer than 40 ns duration will be required to activate the reset function
in the device.
2.1.2
Software Reset
The internal registers of each UART can be reset by writing to the RESET register in the Device Configuration
Registers. For more details, see the RESET register description on page 24.
2.2
UART Channel Selection
A LOW on the chip select pin, CS#, allows the user to select one of the UART channels to configure, send
transmit data and/or unload receive data to/from the UART. When address line A7 = 0, address lines A6:A4
are used to select one of the eight channels. See Table 1 below for UART channel selection.
2.3
Simultaneous Write to All Channels
During a write cycle, the setting of the Device Configuration register REGB (See Table 8) bit-0 to a logic 1 will
override the channel selection of address A6:A4 and allow a simultaneous write to all 4 UART channels when
any channel is written to. This functional capability allow the registers in all 4 UART channels to be modified
concurrently, saving individual channel initialization time. Caution should be considered, however, when using
this capability. Any in-process serial data transfer may be disrupted by changing an active channel’s mode.
Also, REGB bit-0 should be reset to a logic 0 before attempting to read from the UART.
TABLE 1: UART CHANNEL SELECTION
A7
A6
A5
A4
FUNCTION
0
Channel 0 Selected
0
1
Channel 1 Selected
0
1
0
Channel 2 Selected
0
1
Channel 3 Selected
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