參數(shù)資料
型號(hào)： XR16V654IQ-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 13/58頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 64B QUAD 100QFP
標(biāo)準(zhǔn)包裝： 66
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 64 字節(jié)
規(guī)程： RS232
電源電壓： 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 托盤
XR16V654/654D
20
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.1
2.11
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 12):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the RTS#
pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.12
Auto RTS Hysteresis
The V654 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt
is generated when the receive FIFO reaches the selected RX trigger level. The RTS# pin will not be forced
HIGH (RTS off) until the receive FIFO reaches one trigger level above the selected trigger level in the trigger
table (Table 12). The RTS# pin will return LOW after the RX FIFO is unloaded to one level below the selected
trigger level. Under the above described conditions, the V654 will continue to accept data until the receive
FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is asserted LOW (RTS On).
FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
TABLE 7: AUTO RTS (HARDWARE) FLOW CONTROL
RX TRIGGER LEVEL
INT PIN ACTIVATION
RTS# DE-ASSERTED (HIGH)
(CHARACTERS IN RX FIFO)
RTS# ASSERTED (LOW)
(CHARACTERS IN RX FIFO)
8
16
0
16
56
8
56
60
16
60
56
Receive Data S hift
R egister (R S R )
R X FIFO 1
16X or 8X or 4X C lock
( DLD[5:4] )
Err
o
rT
a
g
s
(64
-se
ts
)
Er
ro
rT
a
g
s
i
n
LS
R
b
it
s
4:
2
R eceive D ata C haracters
D ata B it
V alidation
Receive
D ata FIF O
Receive
Data
Receive Data
B yte and E rrors
R H R Interrupt (IS R bit-2) program m ed for
desired FIFO trigger level.
FIFO is E nabled by F C R bit-0=1
R TS # de-asserts w hen data fills above the flow
control trigger level to suspend rem ote transm itter.
E nable by E FR bit-6=1, M C R bit-1.
R TS# re-asserts w hen data falls below the flow
control trigger level to restart rem ote transm itter.
E nable by E FR bit-6=1, M C R bit-1.
64 bytes by 11-bit w ide
FIFO
Trigger=16
D ata falls to
8
D ata fills to
56
E xam ple
: - R X FIFO trigger level selected at 16 bytes
(See N ote Below )
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