參數資料
型號: XR16M580IB25-F
廠商: Exar Corporation
文件頁數: 35/56頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B 25BGA
標準包裝: 714
特點: *
通道數: 1,UART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 25-WFBGA
供應商設備封裝: 25-BGA(3x3)
包裝: 托盤
XR16M580
40
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
REV. 1.0.0
4.16
Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 3-5, MCR bits 5-7, and DLD
to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.
This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it
is recommended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 3-5, MCR bits 5-
7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 3-5,
and MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the EFR[3:0] register bits to be modified by the user.
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
No TX and RX flow control (default and reset)
0
X
No transmit flow control
1
0
X
Transmit Xon1, Xoff1
0
1
X
Transmit Xon2, Xoff2
1
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
0
No receive flow control
X
1
0
Receiver compares Xon1, Xoff1
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
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