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參數(shù)資料
型號： XR16M2750IM48-F
廠商： Exar Corporation
文件頁數(shù)： 23/53頁
文件大?。?/td> 0K
描述： IC UART FIFO 64B DUAL 48TQFP
標準包裝： 250
特點： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應商設備封裝： 48-TQFP（7x7）
包裝： 托盤
XR16M2750
3
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
NAME
32-QFN
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
18
19
20
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
2
1
32
31
30
29
28
27
3
2
1
48
47
46
45
44
I/O
Data bus lines [7:0] (bidirectional).
IOR#
14
19
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
IOW#
12
15
I
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CSA#
7
10
I
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
CSB#
8
11
I
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
INTA
22
30
O
UART channel A Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
INTB
21
29
O
UART channel B Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
TXRDYA#
-
43
O
UART channel A Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel A. See
Table 2. If it is not
used, leave it unconnected.
RXRDYA#
-
31
O
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. See
Table 2. If it is not
used, leave it unconnected.
TXRDYB#
-
6
O
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
Table 3. If it is not
used, leave it unconnected.
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相關代理商/技術參數(shù)
參數(shù)描述
XR16M2751 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE
XR16M2751_07 制造商:EXAR 制造商全稱:EXAR 功能描述:1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
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XR16M2751IM-0B-EB 功能描述:界面開發(fā)工具 Eval Board for XR16M2751IM Series RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XR16M2751IM48 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE
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