REV. 1.2.3 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 5 TXB 8 O UART channel B Transmit Data or infrared encoder data. Stand" />
參數(shù)資料
型號: XR16L2751IM-F
廠商: Exar Corporation
文件頁數(shù): 45/50頁
文件大小: 0K
描述: IC UART FIFO 64B DUAL 48TQFP
標(biāo)準包裝: 250
特點: *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.25 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
其它名稱: 1016-1452
XR16L2751IM-F-ND
XR16L2751
REV. 1.2.3
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
5
TXB
8
O
UART channel B Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.
RXB
4
I
UART channel B Receive Data or infrared receive data. Normal receive data input
must idle HIGH. The infrared receiver pulses typically idles LOW but can be inverted
by software control prior going in to the decoder, see MCR[6] and FCTR[2].
RTSB#
22
O
UART channel B Request-to-Send (active low) or general purpose output. This port
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3] and EMSR[3].
CTSB#
23
I
UART channel B Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
DTRB#
35
O
UART channel B Data-Terminal-Ready (active low) or general purpose output.
DSRB#
20
I
UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART
CDB#
16
I
UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART
RIB#
21
I
UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
OP2B#
9
O
Output Port 2 Channel B - The output state is defined by the user and through the
software setting of MCR[3]. When MCR[3] is set to a logic 1, INTB is set to the level
mode and OP2B# output LOW. When MCR[3] is set to a logic 0, INTB is set to the
three state mode and OP2B# is HIGH. See MCR[3]. This output must not be used as
a general output when the interrupt output is used else it will disturb the INTB output
functionality.
ANCILLARY SIGNALS
XTAL1
13
I
Crystal or external clock input. This input is not 5V tolerant.
XTAL2
14
O
Crystal or buffered clock output. This output may be use to drive a clock buffer which
can drive other device(s).
PwrSave
12
I
PowerSave (active high). This feature isolates the 2751’s data bus interface from the
host preventing other bus activities that cause higher power drain during sleep mode.
See Sleep Mode with Auto Wake-up and PowerSave Feature section for details.
16/68#
24
I
Intel or Motorola Bus Select.
When 16/68# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus
type of interface.
When 16/68# pin is LOW, 68 or Motorola mode, the device will operate in the Motor-
ola bus type of interface.
CLKSEL
25
I
Baud-Rate-Generator Input Clock Prescaler Select for channel A and B. This input is
only sampled during power up or a reset. Connect to VCC for divide by 1 and GND
for divide by 4. MCR[7] can override the state of this pin following a reset or initializa-
tion. See MCR bit-7 and
Figure 6 in the Baud Rate Generator section.
Pin Description
NAME
48-TQFP
PIN #
TYPE
DESCRIPTION
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