REV. 1.2.1 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 3 PIN DESCRIPTIONS Pin Description NAME
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� XR16L2750IM-F
寤犲晢锛� Exar Corporation
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鎻忚堪锛� IC UART FIFO 64B DUAL 48TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 250
鐗归粸(di菐n)锛� *
閫氶亾鏁�(sh霉)锛� 2锛孌UART
FIFO's锛� 64 瀛楃瘈(ji茅)
瑕�(gu墨)绋嬶細 RS232锛孯S485
闆绘簮闆诲锛� 2.25 V ~ 5.5 V
甯惰嚜鍕�(d貌ng)娴侀噺鎺у埗鍔熻兘锛� 鏄�
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甯禖MOS锛� 鏄�
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 48-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 48-TQFP锛�7x7锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 1016-1280
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XR16L2750
REV. 1.2.1
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
3
PIN DESCRIPTIONS
Pin Description
NAME
44-PLCC
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
29
30
31
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
3
2
1
48
47
46
45
44
I/O
Data bus lines [7:0] (bidirectional).
IOR#
24
19
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
IOW#
20
15
I
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CSA#
16
10
I
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
CSB#
17
11
I
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
INTA
33
30
O
UART channel A Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
INTB
32
29
O
UART channel B Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
TXRDYA#
1
43
O
UART channel A Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel A. See
Table 2. If it is not
used, leave it unconnected.
RXRDYA#
34
31
O
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. See
Table 2. If it is not
used, leave it unconnected.
TXRDYB#
12
6
O
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
Table 3. If it is not
used, leave it unconnected.
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XR16L2751 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
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XR16L2751CM 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
XR16L2751CM-0A-EB 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 Supports L2751 48 ld TQFP, ISA Interface RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel