tolerance) connected externally between the XTAL1 and XTAL2 pins (" />
參數(shù)資料
型號： XR16C864CQTR-F
廠商： Exar Corporation
文件頁數(shù)： 5/51頁
文件大?。?/td> 0K
描述： IC UART FIFO 128B QUAD 100QFP
標準包裝： 500
特點： *
通道數(shù)： 4，QUART
FIFO's： 128 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 100-BQFP
供應商設(shè)備封裝： 100-QFP（14x20）
包裝： 帶卷 (TR)
XR16C864
13
REV. 2.2.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4). Typical standard crystal
frequencies are: 1.8432, 3.6864, 7.3728, 14.7456, 18.432, and 22.1184 MHz. Alternatively, an external clock
can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates.
Typical oscillator connections are shown in Figure 4. For further reading on oscillator circuit please see
application note DAN108 on EXAR’s web site.
2.11
Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external
clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a
programmable divisor between 1 and (216 -1) to obtain a 16X sampling rate clock of the serial data rate. The
sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling.
Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
FIGURE 5. BAUD RATE GENERATOR AND PRESCALER
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=1
OUTPUT Data Rate
MCR Bit-7=0
(DEFAULT)
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM
PROGRAM
VALUE (HEX)
DLL
PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
100
600
1200
2400
4800
9600
19.2k
38.4k
57.6k
115.2k
230.4k
400
2400
4800
9600
19.2k
38.4k
76.8k
153.6k
230.4k
460.8k
921.6k
2304
384
192
96
48
24
12
6
4
2
1
900
180
C0
60
30
18
0C
06
04
02
01
09
01
00
80
C0
60
30
18
0C
06
04
02
01
0
X T A L 1
X T A L 2
C ry s ta l
O s c /
B u ffe r
M C R B it-7 = 0
(d e fa u lt)
M C R B it-7 = 1
D L L a n d D L M
R e g iste rs
P re s c a le r
D iv id e b y 1
P re s c a le r
D iv id e b y 4
1 6 X
S a m p lin g
R a te C lo c k to
T ra n s m itte r
B a u d R a te
G e n e ra to r
L o g ic
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