REV. 2.3.1 2.97V TO 5.5V UART WITH 128-BYTE FIFO 7 Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. Factory" />
參數(shù)資料
型號: XR16C850IJ-F
廠商: Exar Corporation
文件頁數(shù): 54/56頁
文件大?。?/td> 0K
描述: IC UART FIFO 128B 44PLCC
標準包裝: 27
特點: *
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱: 1016-1568-5
1016-1568-5-ND
1016-1657
XR16C850IJ-F-ND
xr
XR16C850
REV. 2.3.1
2.97V TO 5.5V UART WITH 128-BYTE FIFO
7
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
Factory Test Mode
For devices with top mark date code of "EC YYWW" and older devices, please note that if IOR# (or IOR) and
IOW# (or IOW) are both asserted simultaneously, the 850 will enter a Factory Test Mode. The most noticeable
Factory Test Mode symptom is the continuous transmission of the same character on the TX pin. This usually
happens during power-up or when another device in the design requires both signals to be asserted
simultaneously (like an SDRAM). A solution to this would be to OR (AND if using active-high signals) the chip
selects with the read and write signals to the XR16C850 as shown below:
For devices with top mark date code of "F2 YYWW" and higher devices, the solution for the Factory Test Mode
given in the figure above has been incorporated into the UART. It will only enter Factory Test Mode when all
three signals (chip select, read and write) are asserted simultaneously.
OP1#/
RS485
38
34
O
Output Port 1 (General purpose output) or RS-485 Direction Control Signal. RS-
485 direction control can be selected when FCTR Bit-3 is set to “1”. During data
transmit cycle, RS485 pin is low. An inverter is usually required before connecting
to RS-485 Transceiver.
RESET
39
35
I
Reset Input (active high). When it is asserted, the UART configuration registers are
reset to default values, see
VCC
44
42
Pwr Power supply input. All inputs are 5V tolerant except for XTAL1 for devices with top
mark date code of "F2 YYWW" and newer. Devices with top mark date code of "EC
YYWW" and older do not have 5V tolerant inputs.
GND
22
18
Pwr Power supply common ground.
NAME
44-PIN
PLCC
48-PIN
TQFP
TYPE
DESCRIPTION
CS2#
IOR#
IOW#
CS0 or CS1
IOR
IOW
(Active Low Signals)
(Active High Signals)
CS#
IOR#
IOW#
CS
IOR
IOW
(from CPU
or PLD)
(from CPU
or PLD)
XR16C850
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