REV. 2.1.3 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 9 2.5 Channel A and B Internal Registers Each UART channel in" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� XR16C2850CM-F
寤犲晢锛� Exar Corporation
鏂囦欢闋佹暩(sh霉)锛� 51/51闋�
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鎻忚堪锛� IC UART FIFO 128B DUAL 48TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 250
鐗归粸锛� *
閫氶亾鏁�(sh霉)锛� 2锛孌UART
FIFO's锛� 128 瀛楃瘈(ji茅)
瑕�(gu墨)绋嬶細 RS232锛孯S485
闆绘簮闆诲锛� 2.97 V ~ 5.5 V
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 48-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 48-TQFP锛�7x7锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 1016-1274
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XR16C2850
REV. 2.1.3
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
9
2.5
Channel A and B Internal Registers
Each UART channel in the 2850 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM), and a user accessible scratchpad register (SPR).
Beyond the general 16C2550 features and capabilities, the 2850 offers enhanced feature registers (EMSR,
FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow
control, Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO
trigger level control, and FIFO level counters. All the register functions are discussed in full detail later in
2.6
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn鈥檛
mean 鈥渄irect memory access鈥� but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the 2850 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the 2850
sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
becomes empty. The following table shows their behavior. Also see Figures 20 through 25.
TABLE 1: CHANNEL A AND B SELECT
CSA#
CSB#
FUNCTION
1
UART de-selected
0
1
Channel A selected
1
0
Channel B selected
0
Channel A and B selected
TABLE 2: TABLE 2TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B
LOW = 1 byte
HIGH = no data
LOW = at least 1 byte in FIFO
HIGH = FIFO empty
HIGH to LOW transition when FIFO reaches
the trigger level, or timeout occurs.
LOW to HIGH transition when FIFO empties.
TXRDY# A/B
LOW = THR empty
HIGH = byte in THR
LOW = FIFO empty
HIGH = at least 1 byte in FIFO
LOW = FIFO has at least 1 empty location
HIGH = FIFO is full
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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