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參數(shù)資料
| 型號(hào)： | XQ4028EX-4HQ240N |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | FPGA, 1024 CLBS, 18000 GATES, 143 MHz, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 304K |
| 代理商： | XQ4028EX-4HQ240N |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
1-800-255-7778XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000E/EX devices unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol
T
WCS
T
WCTS
T
WPS
T
WPTS
T
ASS
T
ASTS
T
AHS
T
AHTS
T
DSS
T
DSTS
T
DHS
T
DHTS
T
WSS
T
WSTS
T
WHS
T
WHTS
T
WOS
T
WOTS
Notes:
1.
Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
2.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Write Operation Description
Address write cycle time (clock K period)
Size
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
-3
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
14.4
14.4
7.2
7.2
2.4
2.4
0
0
3.2
1.9
0
0
2.0
2.0
0
0
8.8
10.3
Max
-
-
1 ms
1 ms
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min
15.0
15.0
7.5
7.5
2.8
2.8
0
0
3.5
2.5
0
0
2.2
2.2
0
0
-
-
Max
-
-
1 ms
1 ms
-
-
-
-
-
-
-
-
-
-
-
-
10.3
11.6
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
D
IN
setup time before clock K
D
IN
hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol
T
WCDS
T
WPDS
T
ASDS
T
AHDS
T
DSDS
T
DHDS
T
WSDS
T
WHDS
T
WODS
Notes:
1.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Write Operation Description
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
D
IN
setup time before clock K
D
IN
hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
Size
(1)
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
-3
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
14.4
7.2
2.5
0
2.5
0
1.8
0
-
Max
Min
15.0
7.5
2.8
0
2.2
0
2.2
0.3
-
Max
1 ms
-
-
-
-
-
-
7.8
1 ms
-
-
-
-
-
-
10.0
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