參數(shù)資料
型號: XQ2V1000-4FG456N
廠商: XILINX INC
元件分類: FPGA
英文描述: QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述: FPGA, 1280 CLBS, 1000000 GATES, 650 MHz, PBGA456
封裝: 1 MM PITCH, MO-151AAJ-1, FBGA-456
文件頁數(shù): 77/128頁
文件大小: 2738K
代理商: XQ2V1000-4FG456N
QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
77
R
PROG_B
Input
Active Low asynchronous reset to configuration logic. This pin has a permanent weak
pull-up resistor.
DONE
Input/Output
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output,
this pin indicates completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the start-up sequence.
M2, M1, M0
Input
Configuration mode selection.
HSWAP_EN
Input
Enable I/O pullups during configuration.
TCK
Input
Boundary Scan Clock.
TDI
Input
Boundary Scan Data Input.
TDO
Output
Boundary Scan Data Output.
TMS
Input
Boundary Scan Mode Select.
PWRDWN_B
Input
(unsupported)
Active Low power-down pin (unsupported).
Driving this pin Low can adversely affect
device operation and configuration.
PWRDWN_B is internally pulled High, which is its
default state. It does not require an external pull-up.
Other Pins
DXN, DXP
N/A
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
V
BATT
RSVD
Input
Decryptor key memory backup supply. (Do not connect if battery is not used.)
N/A
Reserved pin - do not connect.
V
CCO
V
CCAUX
V
CCINT
GND
Input
Power-supply pins for the output drivers (per bank).
Input
Power-supply pins for auxiliary circuits.
Input
Power-supply pins for the internal core logic.
Input
Ground.
Notes:
1.
All dedicated pins (JTAG and configuration) are powered by V
CCAUX
(independent of the bank V
CCO
voltage).
Table 74:
QPro Virtex-II Pin Definitions
(Continued)
Pin Name
Direction
Description
ds122_1_1.fm Page 77 Wednesday, January 7, 2004 9:15 PM
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