參數(shù)資料
型號： XPC850ZT80BU
廠商： Freescale Semiconductor
文件頁數(shù)： 48/72頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC 80MHZ 256-PBGA
標準包裝： 60
系列： MPC8xx
處理器類型： 32-位 MPC8xx PowerQUICC
速度： 80MHz
電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應商設備封裝： 256-PBGA（23x23）
包裝： 托盤
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
52
Freescale Semiconductor
CPM Electrical Characteristics
8.6
SCC in NMSI Mode Electrical Specifications
Table 18 provides the NMSI external clock timing.
Table 19 provides the NMSI internal clock timing.
Table 18. NMSI External Clock Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
100
RCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this
table)
1
The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater than or equal to 2.25/1.
1/SYNCCLK
—
ns
101
RCLKx and TCLKx width low
1/SYNCCLK +5
—
ns
102
RCLKx and TCLKx rise/fall time
—
15.00
ns
103
TXDx active delay (from TCLKx falling edge)
0.00
50.00
ns
104
RTSx active/inactive delay (from TCLKx falling edge)
0.00
50.00
ns
105
CTSx setup time to TCLKx rising edge
5.00
—
ns
106
RXDx setup time to RCLKx rising edge
5.00
—
ns
107
RXDx hold time from RCLKx rising edge 2
2
Also applies to CD and CTS hold time when they are used as an external sync signal.
5.00
—
ns
108
CDx setup time to RCLKx rising edge
5.00
—
ns
Table 19. NMSI Internal Clock Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
100
RCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this table)
1
The ratios SyncCLK/RCLKx and SyncCLK/TCLK1x must be greater or equal to 3/1.
0.00
SYNCCLK/3
MHz
102
RCLKx and TCLKx rise/fall time
—
ns
103
TXDx active delay (from TCLKx falling edge)
0.00
30.00
ns
104
RTSx active/inactive delay (from TCLKx falling edge)
0.00
30.00
ns
105
CTSx setup time to TCLKx rising edge
40.00
—
ns
106
RXDx setup time to RCLKx rising edge
40.00
—
ns
107
RXDx hold time from RCLKx rising edge 2
2
Also applies to CD and CTS hold time when they are used as an external sync signals.
0.00
—
ns
108
CDx setup time to RCLKx rising edge
40.00
—
ns
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