參數(shù)資料
型號(hào)： XPC8240LVV200E
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 41/52頁(yè)
文件大小： 0K
描述： IC MPU INTEGRATED 200MHZ 352TBGA
標(biāo)準(zhǔn)包裝： 24
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 200MHz
電壓： 2.5V
安裝類型： 表面貼裝
封裝/外殼： 352-LBGA
供應(yīng)商設(shè)備封裝： 352-TBGA（35x35）
包裝： 托盤
46
MPC8240 Integrated Processor Hardware Specifications
Document Revision History
0.3
Removed “PowerPC Platform compliant” from first sentence on cover sheet.
Changed PCI 2.1—’compatible’ to ‘compliant’ in Section 1.2.
Updated Table 5 and its notes with preliminary power-consumption information.
Updated Table 6, removing 266 MHz frequency information.
Made corrections to Table 7.
Items 5a and 5b were changed to correct values for 66-MHz PCI_SYNC_IN.
OSC_IN Frequency Stability spec from 1000 to 100 ppm.
Table 9:
Changed item 12b1 from 8.0 to 7.0 ns.
Added item 12b3, Output Valid for ROM accesses.
Table 11, item 2, “KAHLUA” terminology replaced with MPC8240.
Added EPIC Serial Interrupt Timing Section with two new figures, causing cross-references to
subsequent figures to be updated.
Updated formatting of pin out in Table 17.
Modified notes section in Table 17:
Split Note 3 into new Notes 3 and 12. Notes 3, 5, and 7 cover internal pull-up resistors active only
during the reset state. Note 12 covers internal pull-up resistors enabled at all times.
Note 11 has been revised.
Added Note 10 to SDA and SCL signals for consistency with theMPC8240 User’s Manual.
Added Note 10 to SMI and TBEN; inputs that should have pull-ups and for consistency with reference
designs.
Added Note 10 to SRESET and CHKSTOP_IN for consistency with Figure 23 (COP Connector)
Added Notes 13 and 14 for output valid specifications dependent upon memory mode.
Added Note 15 for pins affected by programmable PCI output valid and hold time.
Added Notes 16 –18 relating to open drain pins.
Figure 18:
Revised 200-MHz column to reflect PCI_SYNC_IN 66-MHz upper limit.
Refs 1E and 1F not usable entries made to match others in the table.
Revised Notes 4 and 5 changing OSC_IN to PCI_SYNC_IN.
Removed 266-MHz column.
Removed Ref 0x06 for dual PLL bypass mode; added it to reserved list in Note 3.
Revised Note 4 describing PLL bypass mode.
Added missing cross-reference in Section 1.7.2 and corrected Schottky reference to the 1N5820 diodes.
Added Section 1.7.2 on power supply sizing.
Modified internal pull-up resistor list in Section 1.7.5 to be consistent with Notes of Table 17; added reset
configuration pin pull-down resistor value recommendation.
Modified Figure 23, COP connector diagram:
Reversed direction of CKSTP_IN arrow to show it going in.
Added a pull-up resistor on TRST.
Changed R-spec device’s VDD range from 2.5–2.625 V to 2.5–2.75 V.
0.4
Modified DLL Lock Range with DLL_EXTEND = 1 equation in Table 7 from 0
≤ (NT
clk/2 – tloop – tfix0) ≤ 7
to 0
≤(NT
clk – Tclk/2 – tloop – tfix0) ≤ 7.
Modified Figure 5 to only show Tloop up to 15 ns, not practical to implement Tloop beyond 15 ns.
Modified DL[0:31] and DH[0:31] signal names to MDL[0:31] and MDH[0:31], respectively, in Table 17 to
be consistent with the Tundra Tsi107 PowerPC host bridge data bus naming convention.
Several active low signal names in Table 17 inadvertently had the overline formatting removed during the
final edit process of the previous revision. The signals are shown correctly with overlines in this version.
Signals affected were: DEVSEL, FRAME, LOCK, PERR, SERR, STOP, TRDY, INTA, FOE, RCS0, RCS1,
SDRAS, SDCAS, WE, AS, HRST_CTRL, HRST_CPU, MCP, SMI, SRESET, CHKSTOP_IN, and MIV.
Table 19. Document Revision History (continued)
Revision
Number
Substantive Change(s)
F
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e
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a
le
S
e
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n
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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