參數(shù)資料
型號： XOSM-533ETFH6050M
廠商： VISHAY DALE
元件分類： XO, clock
英文描述： CRYSTAL OSCILLATOR, CLOCK, 50 MHz, HCMOS OUTPUT
封裝： ROHS COMPLIANT, ULTRA MINIATURE PACKAGE-4
文件頁數(shù)： 1/3頁
文件大?。?/td> 88K
代理商： XOSM-533ETFH6050M
Document Number: 35060
Revision: 05-Mar-07
For technical questions contact: frequency@vishay.com
www.vishay.com
37
Surface Mount Oscillator
XOSM-533
Vishay Dale
FEATURES
5 x 3.2 x 1.3 Miniature Package
Tri-state enable/disable
HCMOS compatible
Tape and Reel
IR Re-flow
3.3 V input voltage
Lead (Pb)-free terminations and RoHS compliant
RoHS
COMPLIANT
The XOSM-533 series is an ultra miniature package clock
oscillator with dimensions 5.0 x 3.2 x 1.3 mm. It is mainly
used in portable PC and telecommunication devices and
equipment.
* Include: 25 oC tolerance, operating temperature range, input voltage change, aging, load change, shock and vibration.
DIMENSIONS
in inches [millimeters]
STANDARD ELECTRICAL SPECIFICATIONS
PARAMETER
Frequency Range
Frequency Stability*
Operating Temperature
Storage Temperature Range
Power Supply Voltage
Aging (First Year)
SYMBOL
F
O
CONDITION
XOSM-533
1.544 MHz ~ 100.000 MHz
± 25 ppm, ± 50 ppm, ± 100 ppm
0 oC ~ 70 oC (- 40 oC ~ + 85 oC option)
- 55 oC ~ + 125 oC
3.3 V ± 10 %
± 5 ppm
8 mA Max
10 mA Max
25 mA Max
35 mA Max
40/60 % (45/55 % Option)
7 ns Max
7 ns Max
90 % V
DD
Min
10 % V
DD
Max
30 pF Max (15 pF typ.)
10 ms Max
Pin 1 = H or open.... output active at pin 3
Pin 1 = L..... high impedance at pin 3
All Condition*
T
OPR
T
STG
V
DD
25 oC ± 3 oC
1.544 MHz to 9.999 MHz
10.000 MHz to 34.999 MHz
35.000 MHz to 49.999 MHz
50.000 MHz to 100.000 MHz
At 1/2 V
DD
10 % V
DD
~ 90 % V
DD
90 % V
DD
~ 10 % V
DD
Supply Current
I
DD
Output Symmetry
Rise Time
Fall Time
Sym
T
r
T
f
V
OH
V
OL
Output Voltage
Output Load
Start-up Time
Pin 1, tri-state function
HCMOS Load
Ts
ORDERING INFORMATION
XOSM-533
MODEL
FREQUENCY STABILITY
AA = 0.0025 % (25 ppm)
A = 0.005 % (50 ppm)
B = 0.01 % (100 ppm) Standard
B
R
OTR
Blank = Standard
R = - 40 °C to + 85 °C
E
ENABLE/DISABLE
E = Disable to Tristate
50 M
FREQUENCY/MHz
e2
JEDEC
LEAD (Pb)-FREE
STANDARD
GLOBAL PART NUMBER
MODEL
FREQUENCY
STABILITY
OTR
ENABLE/
DISABLE
PACKAGE
CODE
OPTIONS
FREQUENCY
PIN
#1
#2
#3
#4
CONNECTION
TRI-STATE/NC
GND
OUTPUT
V
DD
#4
0.130 ± 0.008 [3.3 ± 0.2]
***note: A 0.01 μF bypass capacitor should be placed between V
DD
(Pin4) and GND (Pin2) to minimize power supply line noise
0[5.0 ± 0.2]
0.051 [1.3 max]
[1.2]
#3
#1
#2
0[1.20 ± 0.1]
0.1 ± 0.003
[2.2]
[1.4]
[0.1
[1.2]
x
O
6
3
C
T
E
A
N
A
5
0
M
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