參數(shù)資料
型號(hào): XE8807AMI026TLF
廠(chǎng)商: Semtech
文件頁(yè)數(shù): 36/143頁(yè)
文件大?。?/td> 0K
描述: IC MCU LOW PWR MTP FLASH 32-TQFP
標(biāo)準(zhǔn)包裝: 1
系列: XE880x
應(yīng)用: 感測(cè)機(jī)
核心處理器: Coolrisc816?
程序存儲(chǔ)器類(lèi)型: 閃存(11 kB)
控制器系列: XE8000
RAM 容量: 512 x 8
接口: UART,USRT
輸入/輸出數(shù): 24
電源電壓: 2.4 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-TQFP
包裝: 標(biāo)準(zhǔn)包裝
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
產(chǎn)品目錄頁(yè)面: 585 (CN2011-ZH PDF)
配用: XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
其它名稱(chēng): XE8807AMI026DKR
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Semtech 2006
www.semtech.com
17-9
XE8806A/XE8807A
The PWM resolution is always 8 bits when the counters used for the PWM signal generation are not cascaded.
PWM0Size(1:0) and PWM1Size(1:0) in the RegCntConfig2 register are used to set the PWM resolution for the
counters A and B or C and D respectively when they are in cascaded mode. The different possible resolutions in
cascaded mode are shown in Table 17-14. Choosing a 16 bit PWM code which is higher than the maximum value
that can be represented by the number of bits chosen for the resolution results in a PWM output which is always
tied to 1.
PwmXsize(1:0)
Resolution
11
16 bits
10
14 bits
01
12 bits
00
10 bits
Table 17-14: Resolution selection in cascaded PWM mode
Small PWM code
Large PWM code
Tper
Thlarge
Tllarge
Thsmall
Tlsmall
Figure 17-3: PWM modulation examples
The period of the PWM signal is given by the formula:
ckcnt
resolution
f
Tper
2
=
The duty cycle ratio DCR of the PWM signal is defined as:
Tper
Th
DCR
=
DCR can be selected between
resolution
2
100
% and 100 %.
DCR in % in function of the RegCntX content(s) is given by the relation:
(
)
+
=
100
,
2
RegCntX
1
100
resolution
MIN
DCR
17.11 Capture function
The 16-bit capture register is provided to facilitate frequency measurements. It provides a safe reading mechanism
for the counters A and B when they are running. When the capture function is active, the processor does not read
anymore the counters A and B directly, but instead reads shadow registers located in the capture block. An
interrupt is generated after a capture condition has been met when the shadow register content is updated. The
capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or
from the external PA(2) or PA(3) ports. Both counters use the same capture condition.
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