參數(shù)資料
型號: XE8000EV120
廠商: Semtech
文件頁數(shù): 23/108頁
文件大小: 0K
描述: BOARD EVAL FOR SX8722I070TRLF
標(biāo)準(zhǔn)包裝: 1
系列: ZoomingADC™
ADC 的數(shù)量: 1
位數(shù): 16
數(shù)據(jù)接口: I²C
工作溫度: -40°C ~ 125°C
已用 IC / 零件: SX8722
已供物品: 板,CD
產(chǎn)品目錄頁面: 585 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: SX8722I070LFDKR-ND - IC ZOOMING ADC 10BIT 16CH 44MLPQ
SX8722I070LFCT-ND - IC ZOOMING ADC 10BIT 16CH 44MLPQ
SX8722I070LFTR-ND - IC ZOOMING ADC 10BIT 16CH 44MLPQ
其它名稱: XM8000EV120
XM8000EV120-ND
ACS - Revision 4.2
October 2008
2008 Semtech Corp.
www.semtech.com
Page 21
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
SX8722
High gain acquisition for sensor interface
8. Serial communication
The serial interface is a read-write 2 wire slave device. The SCL wire carries the clock information and SDA carries the data.
The output drivers on the bus are open drain current sinks.
The SCL wire is controlled by the master on the bus. Since the SX8722 is fairly slow, it may stretch the low clock phase
when required. The SDA wire is controlled by the master or the slave depending on the operation.
SDA only changes while the clock signal is low except for the (repeated) start or stop conditions.
The (repeated) start condition for the transmission is a high to low transition on SDA while SCL is high. The stop condition is
a low to high transition while SCL is high.
To read data from the SX8722, the master has to send successively a start bit, the slave address, a write bit. If the slave
address corresponds to the address of the SX8722 and the preceding operation is completed, the SX8722 sends an
acknowledge bit. The master then sends the read command which is acknowledged by the salve, the memory address that
it would like to read which is also acknowledged by the slave. The master issues a repeated start, repeats the slave address
and read bit. The slave acknowledges and returns the data to the master. The master terminates the communication by a
"not acknowledge" and a stop bit.
To write data to the SX8722, the format is very similar. Only the data direction is different and the acknowledgement of the
slave after the data reception.
8.1. Write data direct
The diagram below shows the write operation.
Figure 7. I2C frame: write register, command 0x10
The diagram below shows the write operation at successive addresses (burst mode)
Figure 8. I2C frame: write burst register, command 0x10
SDA
S
T
A
R
T
DEVICE
ADDRESS
M
S
B
L
S
B
A
C
K
W
R
I
T
E
S
T
O
P
REGISTER
ADDRESS
REGISTER
VALUE
A
C
K
A
C
K
COMMAND
A
C
K
SDA
S
T
A
R
T
S
T
O
P
DEVICE
ADDRESS
M
S
B
L
S
B
A
C
K
W
R
I
T
E
A
C
K
REGISTER
ADDRESS
REGISTER
VALUE (n)
A
C
K
A
C
K
REGISTER
VALUE (n + x)
A
C
K
COMMAND
Not
Recommended
for
New
Designs
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