參數(shù)資料
型號(hào)： XE3005I033
廠商： Electronic Theatre Controls, Inc.
元件分類： Codec
英文描述： Low-Power Audio CODEC
中文描述： 低功耗音頻CODEC
文件頁(yè)數(shù)： 6/32頁(yè)
文件大?。?/td> 465K
代理商： XE3005I033
Data Sheet
XE3005/XE3006
6
D0212-116
2.1.3
DAC Signal Channel
The DAC is based on a multi bit sigma-delta modulator, which operates at a frequency of 8 times the sampling
rate. The outputs of the modulator are 2’s complement words of 6 bit. A pulse-width modulator (PWM) converts
the 6 bit words into 2 single bit streams at 256 times the sampling frequency. Finally the 2 bit streams are
supplied to the power amplifier. The Power Amplifier is a Class D amplifier, which offers higher efficiency than the
traditional Class AB topologies. It uses a three-state unbalanced PWM. This means that both channels of the PA
(AOUTP and AOUTN) will not switch at the same time, therefore the outputs are not purely differential (see figure
5 and 6)
From Serial Audio
Interface
P
N
bit streams
@ 256xFsync
Interpolator
&
Modulator
dac_in(15:0)
@ Fsync
pwm_in(5:0)
@ 8xFsync
Power
Amplifier
s
s = 1 s = 0
P
N
P
N
VSSPA
VDDPA
Pulse Width
Modulator
AOUTP
AOUTN
XE3005/6
Figure 5: DAC block diagram
Figure 6 shows the relation of input and output samples of the PWM (The timing diagram is not to scale in the
time-axis).
pwm_in(5:0) = -1
pwm_in(5:0) = 1
pwm_in(5:0) = 0
1
0
P
N
OUTP-OUTN
1/(256 x Fsync)
2/(256 x Fsync)
pwm_in(5:0) = 2
1/(8 x Fsync)
1
0
VDDPA
VSSPA
-VDDPA
1/(256 x Fsync)
Figure 6: examples PWM in and out (not to scale)
The DAC receives 16-bit wide 2’s complement format through the Serial Audio Interface. The protocol can be
selected through register J. The complete DAC and PA amplifier chain can be powered-down through register I.
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