參數(shù)資料
型號(hào)： XCV812E-8FG900C
廠商： XILINX INC
元件分類： FPGA
英文描述： Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
中文描述： FPGA, 4704 CLBS, 254016 GATES, 416 MHz, PBGA900
封裝： PLASTIC, FBGA-900
文件頁數(shù)： 73/116頁
文件大?。?/td> 1087K
代理商： XCV812E-8FG900C
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
19
R
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
CLKDLLHF
CLKDLL
Units
Description
Symbol
F
CLKIN
Min
Max
Min
Max
Input Clock Period Tolerance
T
IPTOL
-
1.0
-
1.0
ns
Input Clock Jitter Tolerance (Cycle to Cycle)
T
IJITCC
-
±
150
-
±
300
ps
Time Required for DLL to Acquire Lock
(6)
T
LOCK
> 60 MHz
-
20
-
20
μ
s
50 - 60 MHz
-
-
-
25
μ
s
40 - 50 MHz
-
-
-
50
μ
s
30 - 40 MHz
-
-
-
90
μ
s
25 - 30 MHz
-
-
-
120
μ
s
Output Jitter (cycle-to-cycle) for any DLL Clock Output
(1)
T
OJITCC
±
60
±
60
ps
Phase Offset between CLKIN and CLKO
(2)
T
PHIO
±
100
±
100
ps
Phase Offset between Clock Outputs on the DLL
(3)
T
PHOO
±
140
±
140
ps
Maximum Phase Difference between CLKIN and CLKO
(4)
T
PHIOM
±
160
±
160
ps
Maximum Phase Difference between Clock Outputs on the DLL
(5)
T
PHOOM
±
200
±
200
ps
Notes:
1.
Output Jitter
is cycle-to-cycle jitter measured on the DLL output clock and is based on a maximum tap delay resolution,
excluding
input clock jitter.
Phase Offset between CLKIN and CLKO
is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding
Output Jitter and input clock jitter.
Phase Offset between Clock Outputs on the DLL
is the worst-case fixed time difference between rising edges of any two DLL
outputs,
excluding
Output Jitter and input clock jitter.
Maximum Phase Difference between CLKIN an CLKO
is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (
excluding
input clock jitter).
Maximum Phase DIfference between Clock Outputs on the DLL
is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (
excluding
input clock jitter).
Add 30% to the value for Industrial grade parts.
2.
3.
4.
5.
6.
相關(guān)PDF資料
PDF描述
XCV812E-8FG900I Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XE0002B DAA with 2/4 Wire Hybrid
XE0017 Low-Profile, V.34 Compatible Telephone Line Interface
XE0020 Telephone Line Interface with Active Line Monitoring
XE0020C Silver Mica Capacitor; Capacitance:300pF; Capacitance Tolerance:+/- 1%; Series:CD15; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.9mm; Leaded Process Compatible:No RoHS Compliant: No
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV812E-8FG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCVR-040L31 制造商:WWP 功能描述:
XCW 10 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT 10MM 制造商:G & J HALL 功能描述:COUNTERSINK, HEXIBIT, 10MM 制造商:G & J HALL 功能描述:COUNTERSINK, HEXIBIT, 10MM; Drill Bit Size Metric:10mm; Overall Length:30.5mm; SVHC:No SVHC (19-Dec-2012); Countersink Angle:90; Drill Bit Type:Countersink; Drill Point Diameter:10mm; External Diameter:10mm; Head Diameter:10mm; ;RoHS Compliant: NA
XCW10 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT
XCW15 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT
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