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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
23
R
FG676 Differential Pin Pairs
Virtex-E Extended Memory devices have differential pin
pairs that can also provide other functions when not used as
a differential pair. A
√
in the AO column indicates that the pin
pair can be used as an asynchronous output for all devices
provided in this package.
Pairs with a note number in the AO column are device
dependent. They can have asynchronous outputs if the pin
pair is in the same CLB row and column in the device. Num-
bers in this column refer to footnotes that indicate which
devices have pin pairs that can be asynchronous outputs.
The Other Functions column indicates alternative func-
tion(s) not available when the pair is used as a differential
pair or differential clock.
Table 4:
FG676 Fine-Pitch BGA Differential Pin Pair
Summary — XCV405E
Pair
Bank
P
Pin
N
Pin
AO
Other
Functions
Global Differential Clock
3
0
E13
B13
NA
IO_DLL_L21N
2
1
C13
F14
NA
IO_DLL_L21P
1
5
AB13
AF13
NA
IO_DLL_L115
N
0
4
AA14
AC14
NA
IO_DLL_L115P
IOLVDS
Total Pairs: 183, Asynchronous Output Pairs: 97
0
0
F7
C4
NA
-
1
0
C5
G8
√
-
2
0
E7
D6
√
VREF
3
0
F8
A4
NA
-
4
0
D7
B5
NA
-
5
0
G9
E8
√
VREF
6
0
F9
A5
√
-
7
0
C7
D8
NA
-
8
0
E9
B7
NA
-
9
0
D9
A7
NA
-
10
0
G10
B8
NA
VREF
11
0
F10
C9
√
-
12
0
E10
A8
NA
-
13
0
D10
G11
√
-
14
0
F11
B10
√
-
15
0
E11
C10
NA
-
16
0
D11
G12
√
-
17
0
F12
C11
√
VREF
18
0
E12
A11
√
-
19
0
C12
D12
NA
-
20
0
H13
A12
NA
VREF
21
1
F14
B13
NA
IO_LVDS_DLL
22
1
F13
E14
NA
-
23
1
A14
D14
NA
VREF
24
1
H14
C14
NA
-
25
1
C15
G14
√
-
26
1
D15
E15
√
VREF
27
1
F15
C16
√
-
28
1
D16
G15
-
-
29
1
A17
E16
√
-
30
1
E17
C17
√
-
31
1
D17
F16
NA
-
32
1
C18
F17
√
-
33
1
G16
A18
√
VREF
34
1
G17
C19
√
-
35
1
B19
D18
NA
-
36
1
E18
D19
NA
-
37
1
B20
F18
√
-
38
1
C20
G19
√
VREF
39
1
E19
G18
√
-
40
1
D20
A21
√
-
41
1
C21
F19
√
VREF
42
1
E20
B22
√
-
43
1
D21
A23
2
-
44
1
E21
C22
√
CS
45
2
E23
F22
√
DIN, D0
46
2
E24
F20
√
-
47
2
G21
G22
2
-
48
2
F24
H20
1
VREF
49
2
E25
H21
1
-
Table 4:
FG676 Fine-Pitch BGA Differential Pin Pair
Summary — XCV405E
Pair
Bank
P
Pin
N
Pin
AO
Other
Functions
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-7BG676C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG676I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG900C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG900I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG404C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-7BG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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