參數(shù)資料
型號(hào)： XCV812E-7BG560C
廠商： XILINX INC
元件分類： FPGA
英文描述： Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
中文描述： FPGA, 4704 CLBS, 254016 GATES, 400 MHz, PBGA560
封裝： PLASTIC, BGA-560
文件頁數(shù)： 70/116頁
文件大?。?/td> 1087K
代理商： XCV812E-7BG560C
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 3 of 4
16
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
Virtex-E Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate,
with
DLL
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate,
without
DLL
Description
(1)
Symbol
Device
(3)
Speed Grade
(2)
Units
Min
-8
-7
-6
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate,
with
DLL.
For data
output
with different standards, adjust
the delays with the values shown in
‘‘IOB Output
Switching Characteristics Standard Adjustments’’
on page 8
.
T
ICKOFDLL
XCV405E
1.0
3.1
3.1
3.1
ns
XCV812E
1.0
3.1
3.1
3.1
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 50% V
CC
threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 2
and
Table 3
.
DLL output jitter is already included in the timing calculation.
2.
3.
Description
(1)
Symbol
Device
Speed Grade
(2)
Units
Min
-8
-7
-6
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate,
without
DLL.
For data
output
with different standards, adjust
the delays with the values shown in
‘‘IOB Output
Switching Characteristics Standard Adjustments’’
on page 8
.
T
ICKOF
XCV405E
1.6
4.5
4.7
4.9
ns
XCV812E
1.8
4.8
5.0
5.2
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 50% V
CC
threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 2
and
Table 3
.
2.
相關(guān)PDF資料
PDF描述
XCV812E-7BG560I Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG676C Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG676I Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG900C Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG900I Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV812E-7BG560I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG676C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG676I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG900C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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