參數(shù)資料
型號(hào): XCV812E-6FG900C
廠商: XILINX INC
元件分類: FPGA
英文描述: Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
中文描述: FPGA, 4704 CLBS, 254016 GATES, 357 MHz, PBGA900
封裝: PLASTIC, FBGA-900
文件頁數(shù): 67/116頁
文件大?。?/td> 1087K
代理商: XCV812E-6FG900C
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
13
R
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Description
(1)
Symbol
Speed Grade
Units
Min
-8
-7
-6
Combinatorial Delays
F operand inputs to X via XOR
T
OPX
0.32
0.68
0.8
0.8
ns, max
F operand input to XB output
T
OPXB
0.35
0.65
0.8
0.9
ns, max
F operand input to Y via XOR
T
OPY
0.59
1.07
1.4
1.5
ns, max
F operand input to YB output
T
OPYB
0.48
0.89
1.1
1.3
ns, max
F operand input to COUT output
T
OPCYF
0.37
0.71
0.9
1.0
ns, max
G operand inputs to Y via XOR
T
OPGY
0.34
0.72
0.8
0.9
ns, max
G operand input to YB output
T
OPGYB
0.47
0.78
1.2
1.3
ns, max
G operand input to COUT output
T
OPCYG
0.36
0.60
0.9
1.0
ns, max
BX initialization input to COUT
T
BXCY
0.19
0.36
0.51
0.57
ns, max
CIN input to X output via XOR
T
CINX
0.27
0.50
0.6
0.7
ns, max
CIN input to XB
T
CINXB
0.02
0.04
0.07
0.08
ns, max
CIN input to Y via XOR
T
CINY
0.26
0.45
0.7
0.7
ns, max
CIN input to YB
T
CINYB
0.16
0.28
0.38
0.43
ns, max
CIN input to COUT output
T
BYP
0.05
0.10
0.14
0.15
ns, max
Multiplier Operation
F1/2 operand inputs to XB output via AND
T
FANDXB
0.10
0.30
0.35
0.39
ns, max
F1/2 operand inputs to YB output via AND
T
FANDYB
0.28
0.56
0.7
0.8
ns, max
F1/2 operand inputs to COUT output via AND
T
FANDCY
0.17
0.38
0.46
0.51
ns, max
G1/2 operand inputs to YB output via AND
T
GANDYB
0.20
0.46
0.55
0.7
ns, max
G1/2 operand inputs to COUT output via AND
T
GANDCY
0.09
0.28
0.30
0.34
ns, max
Setup and Hold Times before/after Clock CLK
CIN input to FFX
T
CCKX
/T
CKCX
0.47 / 0
1.0 / 0
1.2 / 0
1.3 / 0
ns, min
CIN input to FFY
T
CCKY
/T
CKCY
0.49 / 0
0.92 / 0
1.2 / 0
1.3 / 0
ns, min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
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XCV812E-6FG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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XCV812E-7BG404I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG556C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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