參數(shù)資料
型號： XCS20XL-4TQ144I
廠商： Xilinx Inc
文件頁數(shù)： 46/83頁
文件大?。?/td> 0K
描述： IC FPGA 3.3V I-TEMP HP 144TQFP
產品變化通告： Product Discontinuation 26/Oct/2011
標準包裝： 60
系列： Spartan®-XL
LAB/CLB數(shù)： 400
邏輯元件/單元數(shù)： 950
RAM 位總計： 12800
輸入/輸出數(shù)： 113
門數(shù)： 20000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 144-LQFP
供應商設備封裝： 144-TQFP（20x20）
Spartan and Spartan-XL FPGA Families Data Sheet
50
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan Family IOB Input Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Symbol
Description
Device
Speed Grade
Units
-4
-3
Min
Max
Min
Max
Setup Times - TTL Inputs(1)
TECIK
Clock Enable (EC) to Clock (IK), no delay
All devices
1.6
-
2.1
-
ns
TPICK
Pad to Clock (IK), no delay
All devices
1.5
-
2.0
-
ns
Hold Times
TIKEC
Clock Enable (EC) to Clock (IK), no delay
All devices
0.0
-
0.9
-
ns
All Other Hold Times
All devices
0.0
-
0.0
-
ns
Propagation Delays - TTL Inputs(1)
TPID
Pad to I1, I2
All devices
-
1.5
-
2.0
ns
TPLI
Pad to I1, I2 via transparent input latch, no delay
All devices
-
2.8
-
3.6
ns
TIKRI
Clock (IK) to I1, I2 (flip-flop)
All devices
-
2.7
-
2.8
ns
TIKLI
Clock (IK) to I1, I2 (latch enable, active Low)
All devices
-
3.2
-
3.9
ns
Delay Adder for Input with Delay Option
TDelay
TECIKD = TECIK + TDelay
TPICKD = TPICK + TDelay
TPDLI = TPLI + TDelay
XCS05
3.6
-
4.0
-
ns
XCS10
3.7
-
4.1
-
ns
XCS20
3.8
-
4.2
-
ns
XCS30
4.5
-
5.0
-
ns
XCS40
5.5
-
5.5
-
ns
Global Set/Reset
TMRW
Minimum GSR pulse width
All devices
11.5
-
13.5
-
ns
TRRI
Delay from GSR input to any Q
XCS05
-
9.0
-
11.3
ns
XCS10
-
9.5
-
11.9
ns
XCS20
-
10.0
-
12.5
ns
XCS30
-
10.5
-
13.1
ns
XCS40
-
11.0
-
13.8
ns
Notes:
1.
Delay adder for CMOS Inputs option: for -3 speed grade, add 0.4 ns; for -4 speed grade, add 0.2 ns.
2.
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
3.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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