參數(shù)資料
型號(hào)： XCS05-4PC84C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 11/83頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 5V C-TEMP 84-PLCC
標(biāo)準(zhǔn)包裝： 15
系列： Spartan®
LAB/CLB數(shù)： 100
邏輯元件/單元數(shù)： 238
RAM 位總計(jì)： 3200
輸入/輸出數(shù)： 61
門數(shù)： 5000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
19
Product Specification
R
Product Obsolete/Under Obsolescence
3-State Long Line Drivers
A pair of 3-state buffers is associated with each CLB in the
array. These 3-state buffers (BUFT) can be used to drive
signals onto the nearest horizontal longlines above and
below the CLB. They can therefore be used to implement
multiplexed or bidirectional buses on the horizontal long-
lines, saving logic resources.
There is a weak keeper at each end of these two horizontal
longlines. This circuit prevents undefined floating levels.
However, it is overridden by any driver.
The buffer enable is an active High 3-state (i.e., an active
Low enable), as shown in Table 11.
Three-State Buffer Example
Figure 18 shows how to use the 3-state buffers to imple-
ment a multiplexer. The selection is accomplished by the
buffer 3-state signal.
Pay particular attention to the polarity of the T pin when
using these buffers in a design. Active High 3-state (T) is
identical to an active Low output enable, as shown in
Figure 17: Detail of Spartan/XL Dedicated Carry Logic
01
M
0
1
01
M
0
1
M
0
3
M
1
M
I
G1
G4
F2
F1
F3
COUT
COUT0
G2
G3
F4
CIN
DS060_17_080400
TO
FUNCTION
GENERATORS
M
Table 11: Three-State Buffer Functionality
IN
T
OUT
X1
Z
IN
0
IN
Figure 18: 3-state Buffers Implement a Multiplexer
DN
DC
DB
DA
ABC
N
Z = (DA A) + (DB B) + (DC C) + (DN N)
~100 k
Ω
"Weak Keeper"
DS060_18_080400
BUFT
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