參數(shù)資料
型號(hào)： XCS05-4PC84C
廠(chǎng)商： XILINX INC
元件分類(lèi)： FPGA
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： FPGA, 100 CLBS, 2000 GATES, 166 MHz, PQCC84
封裝： PLASTIC, LCC-84
文件頁(yè)數(shù)： 52/66頁(yè)
文件大?。?/td> 809K
代理商： XCS05-4PC84C
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-52
DS060 (v1.5) March 2, 2000
Spartan-XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values are expressed in nanoseconds unless
otherwise noted.
Pin Descriptions
There are three types of pins in the Spartan/XL devices:
Permanently dedicated pins
User I/O pins that can have special functions
Unrestricted user-programmable I/O pins.
Before and during configuration, all outputs not used for the
configuration process are 3-stated with the I/O pull-up
resistor network activated. After configuration, if an IOB is
unused it is configured as an input with the I/O pull-up
resistor network remaining activated.
Any user I/O can be configured to drive the Global
Set/Reset net GSR or the global three-state net GTS. See
“
Global Signals: GSR and GTS
”
on page 18
for more infor-
mation.
Device pins for Spartan/XL devices are described in
Table 18
.
Speed Grade
-5
-4
Units
Description
Symbol
Device
Min
Max
Min
Max
Propagation Delays
Clock (OK) to Pad, fast
Output (O) to Pad, fast
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid, fast
Output (O) to Pad via Output Mux, fast
Select (OK) to Pad via Output Mux, fast
For Output SLOW option add
T
OKPOF
T
OPF
T
TSHZ
T
TSONF
T
OFPF
T
OKFPF
T
SLOW
All devices
All devices
All devices
All devices
All devices
All devices
All devices
3.2
2.5
2.8
2.6
3.7
3.3
1.5
3.7
2.9
3.3
3.0
4.4
3.9
1.7
ns
ns
ns
ns
ns
ns
ns
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
T
OOK
T
OKO
T
ECOK
T
OKEC
All devices
All devices
All devices
All devices
0.5
0.0
0.0
0.1
0.5
0.0
0.0
0.2
ns
ns
ns
ns
Global Set/Reset
Minimum GSR pulse width
T
MRW
T
RPO
All devices
10.5
11.5
ns
Delay from GSR input to any Pad
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
11.9
12.4
12.9
13.9
14.9
14.0
14.5
15.0
16.0
17.0
ns
ns
ns
ns
ns
Note 1: Output timing is measured at ~50% V
threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited
output rise/fall times are approximately two times longer than fast output rise/fall times.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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