參數(shù)資料
型號： XCS05-3VQ84C
廠商： Xilinx, Inc.
英文描述： Switch Mode Power Supply; Output Voltage:6VDC; Output Power Max:600W; Number of Outputs:5; Supply Voltage Max:264VAC; Supply Voltage Min:85VAC
中文描述： 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列
文件頁數(shù)： 31/66頁
文件大?。?/td> 809K
代理商： XCS05-3VQ84C
R
DS060 (v1.5) March 2, 2000
Powered by ICminer.com Electronic-Library Service CopyRight 2003
4-31
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Delaying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See
Figure 30 on page 30
.)
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
rise time is excessive or poorly defined. As long as PRO-
GRAM is Low, the FPGA keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the begin-
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output. The Spar-
tan/XL PROGRAM pin has a permanent weak pull-up.
Avoid holding PROGRAM Low for more than 500
μ
s.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the
FPGA to wait after completing the configuration memory
clear operation. When INIT is no longer held Low externally,
the device determines its configuration mode by capturing
the state of the Mode pins, and is ready to start the config-
uration process. A master device waits up to an additional
300
μ
s to make sure that any slaves in the optional daisy
chain have seen that INIT is High.
Configuration Through the Boundary Scan
Pins
Spartan/XL devices can be configured through the bound-
ary scan pins. The basic procedure is as follows:
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
Issue the CONFIG command to the TMS input
Wait for INIT to go High
Sequence the boundary scan Test Access Port to the
SHIFT-DR state
Toggle TCK to clock data into TDI pin.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
For more detailed information, refer to the Xilinx application
note, "
Boundary Scan in FPGA Devices
." This application
note applies to Spartan and Spartan-XL devices.
相關PDF資料
PDF描述
XCS05XL-3VQ84C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-4VQ84C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-4VQ84C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-4BG100C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-4PQ100C Spartan and Spartan-XL Families Field Programmable Gate Arrays
相關代理商/技術參數(shù)
參數(shù)描述
XCS05-3VQ84I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-4BG100C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-4BG100I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-4BG144C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-4BG144I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*