參數(shù)資料
型號(hào)： XCS05-3VQ100C
廠(chǎng)商： XILINX INC
元件分類(lèi)： FPGA
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： FPGA, 100 CLBS, 2000 GATES, 125 MHz, PQFP100
封裝： PLASTIC, VQFP-100
文件頁(yè)數(shù)： 53/66頁(yè)
文件大?。?/td> 809K
代理商： XCS05-3VQ100C
R
DS060 (v1.5) March 2, 2000
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4-53
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 18: Pin Descriptions
Pin Name
Permanently Dedicated Pins
I/O
During
Config.
I/O
After
Config.
Pin Description
VCC
X
X
Eight or more (depending on package) connections to the nominal +5V supply voltage
(+3.3V for Spartan-XL devices). All must be connected, and each must be decoupled
with a 0.01
–
0.1
μ
F capacitor to Ground.
Eight or more (depending on package type) connections to Ground. All must be con-
nected.
During configuration, Configuration Clock (CCLK) is an output in Master mode and is an
input in Slave mode. After configuration, CCLK has a weak pull-up resistor and can be
selected as the Readback Clock. There is no CCLK High or Low time restriction on
Spartan/XL devices, except during Readback. See
“
Violating the Maximum High and
Low Time Specification for the Readback Clock
”
on page 32
for an explanation of this
exception.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on DONE
can be configured to delay the global logic initialization and the enabling of outputs.
The optional pull-up resistor is selected as an option in the program that creates the con-
figuration bitstream. The resistor is included by default.
PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-
ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
finishes the current clear cycle and executes another complete clear cycle, before it
goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled
up to VCC.
The Mode input(s) are sampled after INIT goes High to determine the configuration
mode to be used.
During configuration, these pins have a weak pull-up resistor. For the most popular con-
figuration mode, Slave Serial, the mode pins can be left unconnected. For Master Serial
mode, connect the Mode/M0 pin directly to system ground.
PWRDWN is an active Low input that forces the FPGA into the Power Down state and
reduces power consumption. When PWRDWN is Low, the FPGA disables all I/O and
initializes all flip-flops. All inputs are interpreted as Low independent of their actual level.
VCC must be maintained, and the configuration data is maintained. PWRDWN halts
configuration if asserted before or during configuration, and re-starts configuration when
removed. When PWRDWN returns High, the FPGA becomes operational by first en-
abling the inputs and flip-flops and then enabling the outputs. PWRDWN has a default
internal pull-up resistor.
User I/O Pins That Can Have Special Functions
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output without a register, after configuration is completed.
To use this pin, place the library component TDO instead of the usual pad symbol. An
output buffer must still be used.
GND
X
X
CCLK
I or O
I
DONE
I/O
O
PROGRAM
I
I
MODE
(Spartan)
M0, M1
(Spartan-XL)
I
X
PWRDWN
I
I
TDO
O
O
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