參數(shù)資料
型號: XCR5128C-7TQ128I
廠商: Xilinx, Inc.
英文描述: 128 Macrocell CPLD with Enhanced Clocking
中文描述: 128個宏單元CPLD增強型時鐘
文件頁數(shù): 3/19頁
文件大小: 281K
代理商: XCR5128C-7TQ128I
R
XCR5128C: 128 Macrocell CPLD with Enhanced Clocking
3
www.xilinx.com
1-800-255-7778
DS042 (v1.3) October 9, 2000
This product has been discontinued. Please see
www.xilinx.com/partinfo/notify/pdn0007.htm
for details.
Logic Block Architecture
Figure 2
illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. The six control terms can individually be
configured as either SUM or PRODUCT terms, and are
used to control the preset/reset and output enables of the
16 macrocells
flip-flops. In addition, two of the control
terms can be used as clock signals (see Macrocell Archi-
tecture section for details). The PAL array consists of a pro-
grammable AND array with a fixed OR array, while the PLA
array consists of a programmable AND array with a pro-
grammable OR array. The PAL array provides a high speed
path through the array, while the PLA array provides
increased product term density.
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin t
PD
of the XCR5128C device
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macro-
cells. The additional propagation delay incurred by a mac-
rocell using one or all 32 PLA product terms is just 2 ns. So
the total pin-to-pin t
PD
for the XCR5128C using six to 37
product terms is 9.5 ns (7.5 ns for the PAL + 2 ns for the
PLA).
ds042.fm Page 3 Monday, October 9, 2000 8:26 PM
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