參數(shù)資料
型號: XCR5128C-7TQ128C
廠商: XILINX INC
元件分類: PLD
英文描述: 128 Macrocell CPLD with Enhanced Clocking
中文描述: EE PLD, 7.5 ns, PQFP128
封裝: PLASTIC, TQFP-128
文件頁數(shù): 6/19頁
文件大?。?/td> 281K
代理商: XCR5128C-7TQ128C
R
XCR5128C: 128 Macrocell CPLD with Enhanced Clocking
DS042 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
6
This product has been discontinued. Please see
www.xilinx.com/partinfo/notify/pdn0007.htm
for details.
Simple Timing Model
Figure 4
shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including t
PD
, t
SU
, and t
CO
. In other competing architec-
tures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device. This
is because the timing models of competing architectures
are very complex and include such things as timing depen-
dencies on the number of parallel expanders borrowed,
sharable expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.
OUTPUT PIN
INPUT PIN
SP00552
t
PD_PAL
= COMBINATORIAL PAL ONLY
t
PD_PLA
= COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
t
SU_PAL
= PAL ONLY
t
SU_PLA
= PAL + PLA
REGISTERED
t
CO
GLOBAL CLOCK
PIN
Figure 4: CoolRunner Timing Model
ds042.fm Page 6 Monday, October 9, 2000 8:26 PM
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