- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375014 > XCR5128C-12TQ128C (XILINX INC) 128 Macrocell CPLD with Enhanced Clocking PDF資料下載
參數(shù)資料
| 型號： | XCR5128C-12TQ128C |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | 128 Macrocell CPLD with Enhanced Clocking |
| 中文描述： | EE PLD, 12 ns, PQFP128 |
| 封裝： | PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 281K |
| 代理商： | XCR5128C-12TQ128C |
R
XCR5128C: 128 Macrocell CPLD with Enhanced Clocking
9
www.xilinx.com
1-800-255-7778
DS042 (v1.3) October 9, 2000
This product has been discontinued. Please see
www.xilinx.com/partinfo/notify/pdn0007.htm
for details.
5V, In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic sys-
tem before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
Design
-
Faster time-to-market
-
Debug partitioning and simplified prototyping
-
Printed circuit board reconfiguration during debug
-
Better device and board level testing
Manufacturing
-
Multi-Functional hardware
-
Reconfigurability for Test
-
Eliminates handling of
“
fine lead-pitch
”
components
for programming
-
Reduced Inventory and manufacturing costs
-
Improved quality and reliability
Field Support
-
Easy remote upgrades and repair
-
Support for field configuration, re-configuration, and
customization
The Xilinx XCR5128C allows for 5V, in-system program-
ming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally-provided supervoltages, so that the XCR5128C
may be easily programmed on the circuit board using only
the 5V supply required by the device for normal operation.
A set of low-level ISP basic commands implemented in the
XCR5128C enable this feature. The ISP commands imple-
mented in the Xilinx XCR5128C are specified in
Table 5
Please note that an ENABLE command must precede all
ISP commands
unless
an ENABLE command has already
been given for a preceding ISP command.
Terminations
The CoolRunner XCR5128C CPLDs are TotalCMOS
Ε
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the lin-
ear region of the CMOS input structures, which can
increase the power consumption of the device. The
XCR5128C CPLDs have programmable on-chip pull-down
resistors on each I/O pin. These pull-downs are automati-
cally activated by the fitter software for all unused I/O pins.
Note that an I/O macrocell used as buried logic that does
not have the I/O pin used for input is considered to be
unused, and the pull-down resistors will be turned on. Xilinx
recommends that any unused I/O pins on the XCR5128C
device be left unconnected.
There are no on-chip pull-down structures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10k
pull-up resistors. These pins can be directly connected to
V
CC
or GND, but using the external pull-up resistors main-
tains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
When using the JTAG/ISP functions, it is also recom-
mended that 10k
pull-up resistors be used on each of the
pins associated with the four mandatory JTAG signals. Let-
ting these signals float can cause the voltage on TMS to
come close to ground, which could cause the device to
enter JTAG/ISP mode at unspecified times. See the appli-
cation notes
JTAG and ISP Overview for Xilinx XPLA1 and
XPLA2 CPLDs
and
Terminating Unused I/O Pins in Xilinx
XPLA1 and XPLA2 CoolRunner
CPLDs
for more informa-
tion.
Table 4: XCR5128C Low-Level JTAG Boundary-Scan Commands
INSTRUCTION
(Instruction Code)
Register Used
Bypass
(1111)
Bypass Register
DESCRIPTION
Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through the selected device to adjacent devices during normal device
operation. The Bypass instruction can be entered by holding TDI at a constant high value
and completing an Instruction-Scan cycle.
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to
be serially shifted out of TDO. The IDCODE instruction permits blind interrogation of the
components assembled onto a printed circuit board. Thus, in circumstances where the
component population may vary, it is possible to determine what components exist in a
product.
Idcode
(0001)
Boundary-Scan Register
ds042.fm Page 9 Monday, October 9, 2000 8:26 PM
相關PDF資料 |
PDF描述 |
|---|---|
| XCR5128C-12TQ128I | 128 Macrocell CPLD with Enhanced Clocking |
| XCR5128C-12VQ100C | 128 Macrocell CPLD with Enhanced Clocking |
| XCR5128C-12VQ100I | 128 Macrocell CPLD with Enhanced Clocking |
| XCR5128C-15TQ128C | 128 Macrocell CPLD with Enhanced Clocking |
| XCR5128C-15TQ128I | 128 Macrocell CPLD with Enhanced Clocking |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCR5128C-12TQ128I | 制造商:XILINX 制造商全稱:XILINX 功能描述:128 Macrocell CPLD with Enhanced Clocking |
| XCR5128C-12VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:128 Macrocell CPLD with Enhanced Clocking |
| XCR5128C-12VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:128 Macrocell CPLD with Enhanced Clocking |
| XCR5128C-15TQ128C | 制造商:XILINX 制造商全稱:XILINX 功能描述:128 Macrocell CPLD with Enhanced Clocking |
| XCR5128C-15TQ128I | 制造商:XILINX 制造商全稱:XILINX 功能描述:128 Macrocell CPLD with Enhanced Clocking |
發(fā)布緊急采購，3分鐘左右您將得到回復。