參數(shù)資料
型號(hào)： XCR5128C-10TQ128I
廠商： XILINX INC
元件分類： PLD
英文描述： 128 Macrocell CPLD with Enhanced Clocking
中文描述： EE PLD, 10 ns, PQFP128
封裝： PLASTIC, TQFP-128
文件頁(yè)數(shù)： 8/19頁(yè)
文件大?。?/td> 281K
代理商： XCR5128C-10TQ128I
R
XCR5128C: 128 Macrocell CPLD with Enhanced Clocking
DS042 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
8
This product has been discontinued. Please see
www.xilinx.com/partinfo/notify/pdn0007.htm
for details.
JTAG Testing Capability
JTAG is the commonly-used acronym for the Boundary
Scan Test (BST) feature defined for integrated circuits by
IEEE Standard 1149.1. This standard defines input/output
pins, logic control functions, and commands which facilitate
both board and device level testing without the use of spe-
cialized test equipment. The Xilinx XCR5128C devices use
the JTAG Interface for In-System Programming/Repro-
gramming. Although only a subset of the full JTAG com-
mand set is implemented (see
Table 4
), the devices are
fully capable of sitting in a JTAG scan chain.
The Xilinx XCR5128C
’
s JTAG interface includes a TAP Port
defined by the IEEE 1149.1 JTAG Specification. As imple-
mented in the Xilinx XCR5128C, the TAP Port includes four
of the five pins (refer to
Table 2
) described in the JTAG
specification: TCK, TMS, TDI, and TDO. The fifth signal
defined by the JTAG specification is TRST* (Test Reset).
TRST* is considered an optional signal, since it is not actu-
ally required to perform BST or ISP. The Xilinx XCR5128C
saves an I/O pin for general purpose use by not implement-
ing the optional TRST* signal in the JTAG interface.
Instead, the Xilinx XCR5128C supports the test reset func-
tionality through the use of its power up reset circuit, which
is included in all Xilinx CPLDs. The pins associated with the
TAP Port should connect to an external pull-up resistor to
keep the JTAG signals from floating when they are not
being used.
In the Xilinx XCR5128C, the four mandatory JTAG pins
each require a unique, dedicated pin on the device. The
devices come from the factory with these I/O pins set to
perform JTAG functions, but through the software, the final
function of these pins can be controlled. If the end applica-
tion will require the device to be reprogrammed at some
future time with ISP, then the pins can be left as dedicated
JTAG functions, which means they are not available for use
as general purpose I/O pins. However, unlike competing
CPLDs, the Xilinx XCR5128C allow the macrocells associ-
ated with these pins to be used as buried logic when the
JTAG/ISP function is enabled. This is the default state for
the software, and no action is required to leave these pins
enabled for the JTAG/ISP functions. If, however, JTAG/ISP
is not required in the end application, the software can
specify that this function be turned off and that these pins
be used as general purpose I/O. Because the devices ini-
tially have the JTAG/ISP functions enabled, the JEDEC file
can be downloaded into the device once, after which the
JTAG/ISP pins will become general purpose I/O. This fea-
ture is good for manufacturing because the devices can be
programmed during test and assembly of the end product
and yet still use all of the I/O pins after the programming is
done. It eliminates the need for a costly, separate program-
ming step in the manufacturing process. Of course, if the
JTAG/ISP function is never required, this feature can be
turned off in the software and the device can be pro-
grammed with an industry-standard programmer, leaving
the pins available for I/O functions.
Table 3
defines the ded-
icated pins used by the four mandatory JTAG signals for
each of the XCR5128C package types.
Table 2: JTAG Pin Description
Pin
Name
Description
TCK
Test Clock Output
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,
respectively.
Serial input pin selects the JTAG instruction mode. TMS should be driven high
during user mode operation.
Serial input pin for instructions and test data. Data is shifted in on the rising edge
of TCK.
Serial output pin for instructions and test data. Data is shifted out on the falling edge
of TCK. The signal is tri-stated if data is not being shifted out of the device.
TMS
Test Mode Select
TDI
Test Data Input
TDO
Test Data Output
Table 3: XCR5128C JTAG Pinout by Package Type
Device
XCR5128C
100-pin VQFP
128-pin TQFP
(Pin Number / Macrocell #)
TMS
15/C15
21/C15
TCK
62/F15
82/F15
TDI
4/B15
8/B15
TDO
73/G15
95/G15
ds042.fm Page 8 Monday, October 9, 2000 8:26 PM
相關(guān)PDF資料
PDF描述
XCR5128C-10VQ100C 128 Macrocell CPLD with Enhanced Clocking
XCR5128C-10VQ100I 128 Macrocell CPLD with Enhanced Clocking
XCR5128C-12TQ128C 128 Macrocell CPLD with Enhanced Clocking
XCR5128C-12TQ128I 128 Macrocell CPLD with Enhanced Clocking
XCR5128C-12VQ100C 128 Macrocell CPLD with Enhanced Clocking
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCR5128C-10VQ100C 制造商:XILINX 制造商全稱:XILINX 功能描述:128 Macrocell CPLD with Enhanced Clocking
XCR5128C-10VQ100I 制造商:XILINX 制造商全稱:XILINX 功能描述:128 Macrocell CPLD with Enhanced Clocking
XCR5128C-12TQ128C 制造商:XILINX 制造商全稱:XILINX 功能描述:128 Macrocell CPLD with Enhanced Clocking
XCR5128C-12TQ128I 制造商:XILINX 制造商全稱:XILINX 功能描述:128 Macrocell CPLD with Enhanced Clocking
XCR5128C-12VQ100C 制造商:XILINX 制造商全稱:XILINX 功能描述:128 Macrocell CPLD with Enhanced Clocking
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*