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參數(shù)資料
| 型號(hào)： | XCR5128 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 128 Macrocell CPLD(128宏單元復(fù)雜可編程邏輯器件) |
| 中文描述： | 128個(gè)宏單元CPLD（128個(gè)宏單元復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 13/20頁(yè) |
| 文件大小： | 132K |
| 代理商： | XCR5128 |
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R
XCR5128: 128 Macrocell CPLD
13
www.xilinx.com
1-800-255-7778
DS041 (v1.4) January 19, 2001
This product has been discontinued. Please see
for details.AC Electrical Characteristics
1
For Commercial Grade Devices
Commercial: 0
°
C
≤
T
AMB
≤
+70
°
C; 4.75V
≤
V
CC
≤
5.25V
Symbol
Parameter
7
10
12
Unit
Min/
Max.
Min.
Max.
Min.
Max.
t
PD_PAL
Propagation delay time, input (or feedback node) to output
through PAL
Propagation delay time, input (or feedback node) to output
through
PAL + PLA
Clock to out (global synchronous clock from pin)
Setup time (from input or feedback node) through PAL
Setup time (from input or feedback node) through PAL + PLA
Hold time
Clock High time
Clock Low time
Input Rise time
Input Fall time
Maximum FF toggle rate
2
1/(t
CH
+ t
CL
)
Maximum internal frequency
2
1/(t
SUPAL
+ t
CF
)
Maximum external frequency
2
1/(t
SUPAL
+ t
CO
)
Output buffer delay time
Input (or feedback node) to internal feedback node delay time
through PAL
Input (or feedback node) to internal feedback node delay time
through PAL+ PLA
Clock to internal feedback node delay time
Delay from valid V
CC
to valid reset
Input to output disable
2, 3
Input to output valid
2
Input to register preset
2
Input to register reset
2
2
7.5
2
10
2
12
ns
t
PD_PLA
3
9.5
3
12
3
14.5
ns
t
CO
t
SU_PAL
t
SU_PLA
t
H
t
CH
t
CL
t
R
t
F
f
MAX1
f
MAX2
f
MAX3
t
BUF
t
PDF_PA L
2
6
2
7
9
7
2
8
8
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
4.5
6.5
10.5
0
0
0
3
3
4
4
4
4
20
20
20
20
20
20
167
111
95
125
80
71
125
69
63
1.5
6
1.5
8.5
1.5
10.5
2
2
2
t
PDF_PL A
3
8
3
10.5
3
13
ns
t
CF
t
INIT
t
ER
t
EA
t
RP
t
RR
Notes:
4.5
50
5.5
50
6.5
50
ns
μ
s
ns
ns
ns
ns
9
9
12
12
12.5
12.5
15
15
15
15
11
11
1. Specifications measured with one output switching. See
Figure 6
and
Table 6
for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output c
l
= 5 pf.
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