參數(shù)資料
型號(hào): XCR5128-7PC84I
廠商: Xilinx, Inc.
英文描述: 128 Macrocell CPLD
中文描述: 128個(gè)宏單元CPLD
文件頁(yè)數(shù): 8/20頁(yè)
文件大?。?/td> 131K
代理商: XCR5128-7PC84I
R
XCR5128: 128 Macrocell CPLD
DS041 (v1.4) January 19, 2001
www.xilinx.com
1-800-255-7778
8
This product has been discontinued. Please see
www.xilinx.com/partinfo/notify/pdn0007.htm
for details.
cated pins are not available for general purpose use. How-
ever, unlike competing CPLD
s, the Xilinx XCR5128 does
allow the macrocell logic associated with these dedicated
pins to be used as buried logic even when JTAG/ISP is
selected.
Table 3
defines the dedicated pins used by the
four mandatory JTAG signals for each of the XCR5128
package types.
JTAG specifications define two sets of commands to sup-
port boundary-scan testing: high-level commands and
low-level commands. High-level commands are executed
via board test software on an a user test station such as
automated test equipment, a PC, or an engineering work-
station (EWS). Each high-level command comprises a
sequence of low level commands. These low-level com-
mands are executed within the component under test, and
therefore must be implemented as part of the TAP Control-
ler design. The set of low-level boundary-scan commands
implemented in the Xilinx XCR5128 is defined in
Table 4
.
By supporting this set of low-level commands, the
XCR5128 allows execution of all high-level boundary-scan
commands.
Table 2: JTAG Pin Description
Pin
TCK
Name
Description
Test Clock Output
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,
respectively. TCK is also used to clock the TAP Controller state machine.
Serial input pin selects the JTAG instruction mode. TMS should be driven high
during user mode operation.
Serial input pin for instructions and test data. Data is shifted in on the rising edge of
TCK.
Serial output pin for instructions and test data. Data is shifted out on the falling edge
of TCK. The signal is tri-stated if data is not being shifted out of the device.
TMS
Test Mode Select
TDI
Test Data Input
TDO
Test Data Output
Table 3: XCR5128 JTAG Pinout by Package Type
Device
PZ5128
84-pin PLCC
100-pin PQFP
100-pin VQFP
128-pin TQFP
160-pin PQFP
(Pin Number / Macrocell #)
TCK
TMS
TDI
TDO
62 / 96 (F15)
64 / 96 (F15)
62 / 96 (F15)
82 / 96 (F15)
99 / 96 (F15)
23 / 48 (C15)
17 / 48 (C15)
15 / 48 (C15)
21 / 48 (C15)
22 / 48 (C15)
14 / 32 (B15)
6 / 32 (B15)
4 / 32 (B15)
8 / 32 (B15)
9 / 32 (B15)
71 / 112 (G15)
75 / 112 (G15)
73 / 112 (G15)
95 / 112 (G15)
112/ 112 (G15)
Table 4: XCR5128 Low-Level JTAG Boundary-Scan Commands
Instruction
(Instruction Code)
Register Used
Sample/Preload
(0010)
Boundary-Scan Register
Description
The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal operation
of the component to be taken and examined. It also allows data values to be loaded onto the
latched parallel outputs of the Boundary-Scan Shift-Register prior to selection of the other
boundary-scan test instructions.
The mandatory EXTEST instruction allows testing of off-chip circuitry and board level
interconnections. Data would typically be loaded onto the latched parallel outputs of
Boundary-Scan Shift-Register using the Sample/Preload instruction prior to selection of the
EXTEST instruction.
Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through the selected device to adjacent devices during normal device
operation. The Bypass instruction can be entered by holding TDI at a constant high value
and completing an Instruction-Scan cycle.
Extest
(0000)
Boundary-Scan Register
Bypass
(1111)
Bypass Register
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