參數(shù)資料
型號(hào): XCR5128-7PC84C
廠(chǎng)商: XILINX INC
元件分類(lèi): PLD
英文描述: 128 Macrocell CPLD
中文描述: EE PLD, 9.5 ns, PQCC84
封裝: PLASTIC, LCC-84
文件頁(yè)數(shù): 3/20頁(yè)
文件大?。?/td> 131K
代理商: XCR5128-7PC84C
R
XCR5128: 128 Macrocell CPLD
3
www.xilinx.com
1-800-255-7778
DS041 (v1.4) January 19, 2001
This product has been discontinued. Please see
www.xilinx.com/partinfo/notify/pdn0007.htm
for details.
Logic Block Architecture
Figure 2
illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. the six control terms can individually be con-
figured as either SUM or PRODUCT terms, and are used to
control the preset/reset and output enables of the 16 mac-
rocells
flip-flops. The PAL array consists of a programma-
ble AND array with a fixed OR array, while the PLA array
consists of a programmable AND array with a programma-
ble OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased
product term density.
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin t
PD
of the XCR5128 device
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macro-
cells. The additional propagation delay incurred by a mac-
rocell using one or all 32 PLA product terms is just 2 ns. So
the total pin-to-pin t
PD
for the XCR5128 using six to 37
product terms is 9.5 ns (7.5 ns for the PAL + 2 ns for the
PLA)
.
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