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R
XCR5128: 128 Macrocell CPLD
DS041 (v1.4) January 19, 2001
www.xilinx.com
1-800-255-7778
10
This product has been discontinued. Please see
www.xilinx.com/partinfo/notify/pdn0007.htm
for details.
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLD
’
s and other integrated cir-
cuits. The Xilinx XCR5128 supports the following methods:
PC parallel port
Workstation or PC serial port
Embedded processor
Automated test equipment
Third party programmers
High-End JTAG and ISP tools
A Boundary-Scan Description Language (BSDL) descrip-
tion of the XCR5128 is also available from Xilinx for use in
test program development. For more details on JTAG and
ISP for the XCR5128, refer to the related application note:
JTAG and ISP in Xilinx CPLDs
.
Table 5: Low Level ISP Commands
Instruction
(Register Used)
Enable
(ISP Shift Register)
Instruction
Code
1001
Description
Enables the Erase, Program, and Verify commands. Using the ENABLE instruction
before the Erase, Program, and Verify instructions allows the user to specify the
outputs the device using the JTAG Boundary-Scan SAMPLE/PRELOAD
command.
Erases the entire EEPROM array. The outputs during this operation can be defined
by user by using the JTAG SAMPLE/PRELOAD command.
Programs the data in the ISP Shift Register into the addressed EEPROM row. The
outputs during this operation can be defined by user by using the JTAG
SAMPLE/PRELOAD command.
Transfers the data from the addressed row to the ISP Shift Register. The data can
then be shifted out and compared with the JEDEC file. The outputs during this
operation can be defined by user by using the JTAG SAMPLE/PRELOAD
command.
Erase
(ISP Shift Register)
Program
(ISP Shift Register)
1010
1011
Verify
(ISP Shift Register)
1100