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| 型號(hào)： | XCR3320-10TQ144C |
| 文件頁(yè)數(shù)： | 3/43頁(yè) |
| 文件大?。?/td> | 396K |
| 代理商： | XCR3320-10TQ144C |
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XPLA2 Fast Module
Each Fast Module consists of four Logic Blocks of 20 mac-
rocells each. Depending on the package, either seven or 12
of the 20 macrocells in each Logic Block are connected to
I/O pins, and the remaining macrocells are used as buried
nodes. These four Logic Blocks are connected together by
the Local Zero Power Interconnect Array (LZIA). The LZIA
is a virtual crosspoint switch that connects the Logic Blocks
to each other and to the GZIA. The feedback from all 80
macrocells, input from the I/O pins, and the 64 bit input bus
from the GZIA are input into the LZIA. The LZIA outputs 36
signals into each Logic Block and 64 signals into the GZIA
(
Figure 2
).
XPLA2 Logic Block Architecture
Figure 3
illustrates the XPLA2 Logic Block architecture.
Each Logic Block contains eight control terms, a PAL array,
a PLA array, and 20 macrocells. The 36 inputs from the
LZIA are available to all control terms and to each product
term in both the PAL and the PLA array. The eight control
terms can individually be configured as either SUM or
PRODUCT terms, and are used to control the asynchro-
nous preset and reset functions of the macrocell registers,
the output enables of the 20 macrocells, and for asynchro-
nous clocking. The PAL array consists of a programmable
AND array with a fixed OR array, while the PLA array con-
sists of a programmable AND array with a programmable
OR array.
Each macrocell has four dedicated product terms from the
PAL array. When additional logic is required, each macro-
cell takes the extra product terms from the PLA array. The
PLA array consists of 32 extra product terms that are
shared between the 20 macrocells of the Logic Block. The
PAL product terms can be connected to the PLA product
terms through either an OR gate or an XOR gate. One input
to the XOR gate can be connected to all the PLA terms,
which provides for extremely efficient logic synthesis. An
eight bit XOR function can be implemented in only 20 prod-
uct terms. Each macrocell can use the output from the OR
gate or the XOR gate in either normal or inverted state.
Figure 2: Xilinx XPLA2 Fast Module
LOGIC
BLOCK
I/O
36
20
36
20
MC0
MC1
MC19
I/O
MC0
MC1
MC19
LOGIC
BLOCK
I/O
36
20
36
20
MC0
MC1
MC19
I/O
MC0
MC1
MC19
LZIA
LOGIC
BLOCK
LOGIC
BLOCK
64
64
SP00656
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PDF描述 |
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| XCR3320-7TQ144C | |
| XCR3320-8TQ144I | |
| XCR3384XLSERIES | 384 Macrocell CPLD |
| XCS05XL-4PC84C | Field Programmable Gate Array (FPGA) |
| XCS05XL-5PC84C | Field Programmable Gate Array (FPGA) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3320-7TQ144C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| XCR3320-8TQ144I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| XCR3384XL | 制造商:XILINX 制造商全稱:XILINX 功能描述:384 Macrocell CPLD |
| XCR3384XL_06 | 制造商:XILINX 制造商全稱:XILINX 功能描述:384 Macrocell CPLD |
| XCR3384XL_07 | 制造商:XILINX 制造商全稱:XILINX 功能描述:384 Macrocell CPLD |
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