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參數(shù)資料
| 型號(hào)： | XCR3064 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 64 Macrocell CPLD(64宏單元復(fù)雜可編程邏輯器件) |
| 中文描述： | 64宏單元CPLD（64宏單元復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大?。?/td> | 124K |
| 代理商： | XCR3064 |
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DS036 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
1
This product has been discontinued. Please see
for details.Features
Industry's first TotalCMOS PLD - both CMOS design
and process technologies
Fast Zero Power (FZP) design technique provides
ultra-low power and very high speed
High speed pin-to-pin delays of 10 ns
Ultra-low static power of less than 50
μ
A
100% routable with 100% utilization while all pins and
all macrocells are fixed
Deterministic timing model that is extremely simple to
use
Four clocks available
Programmable clock polarity at every macrocell
Support for asynchronous clocking
Innovative XPLA
architecture combines high speed
with extreme flexibility
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Logic expandable to 37 product terms
PCI compliant
Advanced 0.5
μ
E
2
CMOS process
Security bit prevents unauthorized access
Design entry and verification using industry standard
and Xilinx CAE tools
Reprogrammable using industry standard device
programmers
Innovative control term structure provides either sum
terms or product terms in each logic block for:
-
Programmable 3-state buffer
-
Asynchronous macrocell register preset/reset
Programmable global 3-state pin facilitates ‘bed of nails'
testing without using logic resources
Available in PLCC, VQFP, and PQFP packages
Available in both commercial and industrial grades
Description
The XCR3064 CPLD (Complex Programmable Logic
Device) is the second in a family of CoolRunner
CPLDs
from Xilinx. These devices combine high speed and zero
power in a 64 macrocell CPLD. With the FZP design tech-
nique, the XCR3064 offers true pin-to-pin speeds of 10 ns,
while simultaneously delivering power that is less than 50
μ
A at standby without the need for
“
turbo-bits
”
or other
power-down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a tech-
nique that has been used in PLDs since the bipolar era)
with a cascaded chain of pure CMOS gates, the dynamic
power is also substantially lower than any other CPLD.
These devices are the first TotalCMOS PLDs, as they use
both a CMOS process technology
and
the patented full
CMOS FZP design technique. For 5V applications, Xilinx
also offers the high speed XCR5064 CPLD that offers
these features in a full 5V implementation.
The Xilinx FZP CPLDs utiize the patented XPLA (eXtended
Programmable Logic Array) architecture. The XPLA archi-
tecture combines the best features of both PLA and PAL
type structures to deliver high speed and flexible logic allo-
cation that results in superior ability to make design
changes with fixed pinouts. The XPLA structure in each
logic block provides a fast 10 ns PAL path with five dedi-
cated product terms per output. This PAL path is joined by
an additional PLA structure that deploys a pool of 32 prod-
uct terms to a fully programmable OR array that can allo-
cate the PLA product terms to any output in the logic block.
This combination allows logic to be allocated efficiently
throughout the logic block and supports as many as 37
product terms on an output. The speed with which logic is
allocated from the PLA array to an output is only 2.5 ns,
regardless of the number of PLA product terms used, which
results in worst case t
PD
's of only 12.5 ns from any pin to
any other pin. In addition, logic that is common to multiple
outputs can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
The XCR3064 CPLDs are supported by industry standard
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,
Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
uses a Xilinx developed tool, XPLA Professional (available
on the Xilinx web site).
The XCR3064 CPLD is reprogrammable using industry
standard device programmers from vendors such as Data
I/O, BP Microsystems, SMS, and others.
0
XCR3064: 64 Macrocell CPLD
DS036 (v1.3) October 9, 2000
0
14*
Product Specification
R
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3064A | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD With Enhanced Clocking |
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| XCR3064A-10PC44I | 制造商:Xilinx 功能描述: |
| XCR3064A-10VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD With Enhanced Clocking |
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