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| 型號： | XCR3032A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 32 Macrocell CPLD with Enhanced Clocking(帶增強時鐘控制的32宏單元復(fù)雜可編程邏輯器件) |
| 中文描述： | 32宏單元CPLD增強型時鐘（帶增強時鐘控制的32個宏單元復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 313K |
| 代理商： | XCR3032A |
R
XCR3032A: 32 Macrocell CPLD with Enhanced Clocking
DS039 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
8
This product has been discontinued. Please see
for details.3.3-Volt, In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic sys-
tem before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
Design
-
Faster time-to-market
-
Debug partitioning and simplified prototyping
-
Printed circuit board reconfiguration during debug
-
Better device and board level testing
Manufacturing
-
Multi-Functional hardware
-
Reconfigurability for test
-
Eliminates handling of
“
fine lead-pitch
”
components
for programming
-
Reduced Inventory and manufacturing costs
-
Improved quality and reliability
Field Support
-
Easy remote upgrades and repair
-
Support for field configuration, re-configuration, and
customization
The Xilinx XCR3032A allows for 3.3V, in-system program-
ming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally-provided supervoltages, so that the XCR3032A
may be easily programmed on the circuit board using only
the 3.3V supply required by the device for normal opera-
tion. A set of low-level ISP basic commands implemented
in the XCR3032A enable this feature. The ISP commands
implemented in the Xilinx XCR3032A are specified in
Table 5
. Please note that an ENABLE command must pre-
cede all ISP commands
unless
an ENABLE command has
already been given for a preceding ISP command.
Terminations
The CoolRunner XCR3032A CPLDs are TotalCMOS
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the lin-
ear region of the CMOS input structures, which can
increase the power consumption of the device. The
XCR3032A CPLDs have programmable on-chip, pull-down
resistors on each I/O pin. These pull-downs are automati-
cally activated by the fitter software for all unused I/O pins.
Note that an I/O macrocell used as buried logic that does
not have the I/O pin used for input is considered to be
unused, and the pull-down resistors will be turned on.
Xilinx
’
recommends that any unused I/O pins on the
XCR3032A device be left unconnected.
There are no on-chip pull-down structures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10k
pull-up resistors. These pins can be directly connected to
V
CC
or GND, but using the external pull-up resistors main-
tains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
When using the JTAG/ISP functions, it is also recom-
mended that 10k
pull-up resistors be used on each of the
four mandatory signals. Letting these signals float can
cause the voltage on TMS to come close to ground, which
could cause the device to enter JTAG/ISP mode at unspec-
ified times. For more details on JTAG and ISP for the
XCR3032A, refer to the related application note:
JTAG and
ISP Overview for Xilinx XPLA 1 and XPLA2 CPLDs.
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLD's and other integrated cir-
cuits. The Xilinx XCR3032A supports the following meth-
ods:
PC parallel port
Workstation or PC serial port
Embedded processor
Automated test equipment
Third party programmers
High-End ISP tools
Table 5: Low Level ISP Commands
Instruction
(Register Used)
Enable
(ISP Shift Register)
Erase
(ISP Shift Register)
Program
(ISP Shift Register)
Verify
(ISP Shift Register)
Instruction Code
Description
1001
Enables the Erase, Program, and Verify commands.
1010
Erases the entire EEPROM array.
1011
Programs the data in the ISP Shift Register into the addressed EEPROM row.
1100
Transfers the data from the addressed row to the ISP Shift Register. The data
can then be shifted out and compared with the JEDEC file. The outputs during
this operation can be defined by the user.
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| XCR3032XL-10CS48I | 功能描述:IC CPLD 3.3V ZERO PWR 48-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
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