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參數(shù)資料
| 型號： | XCR3032-12VQ44I |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | 32 Macrocell CPLD |
| 中文描述： | EE PLD, 15 ns, PQFP44 |
| 封裝： | PLASTIC, VQFP-44 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 209K |
| 代理商： | XCR3032-12VQ44I |
R
XCR3032: 32 Macrocell CPLD
DS038 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
4
This product has been discontinued. Please see
www.xilinx.com/partinfo/notify/pdn0007.htm
for details.
Macrocell Architecture
Figure 3
shows the architecture of the macrocell used in
the CoolRunner family. The macrocell consists of a flip-flop
that can be configured as either a D- or T-type. A D-type
flip-flop is generally more useful for implementing state
machines and data buffering. A T-type flip-flop is generally
more useful in implementing counters. All CoolRunner
family members provide both synchronous and asynchro-
nous clocking and provide the ability to clock off either the
falling or rising edges of these clocks. These devices are
designed such that the skew between the rising and falling
edges of a clock are minimized for clocking integrity. There
are two clocks (CLK0 and CLK1) available on the
XCR3032 device. Clock 0 (CLK0) is designated as the
"synchronous" clock and must be driven by an external
source. Clock 1 (CLK1) can either be used as a synchro-
nous clock (driven by an external source) or as an asyn-
chronous clock (driven by a macrocell equation). The
timing for asynchronous clocks is different in that the t
CO
time is extended by the amount of time that it takes for the
signal to propagate through the array and reach the clock
network, and the t
SU
time is reduced.
Two of the control terms (CT0 and CT1) are used to control
the Preset/Reset of the macrocell's flip-flop. The Pre-
set/Reset feature for each macrocell can also be disabled.
Note that the Power-on Reset leaves all macrocells in the
"zero" state when power is properly applied. The other four
control terms (CT2-CT5) can be used to control the Output
Enable of the macrocell's output buffers. The reason there
are as many control terms dedicated for the Output Enable
of the macrocell is to insure that all CoolRunner devices are
PCI compliant. The macrocell's output buffers can also be
always enabled or disabled. All CoolRunner devices also
provide a Global 3-state (GTS) pin, which, when enabled
and pulled Low, will 3-state all the outputs of the device.
This pin is provided to support "In-Circuit Testing" or
"Bed-of-Nails
”
testing.
There are two feedback paths to the ZIA: one from the
macrocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA feedback path after the output buffer is the I/O
pin ZIA path. When the macrocell is used as an output, the
output buffer is enabled, and the macrocell feedback path
can be used to feedback the logic implemented in the mac-
rocell. When the I/O pin is used as an input, the output
buffer will be 3-stated and the input signal will be fed into
the ZIA via the I/O feedback path, and the logic imple-
mented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated.
Terminations
The CoolRunner XCR3032 CPLDs are TotalCMOS
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. The XCR3032 devices
do not have on-chip termination circuits, so it is recom-
mended that unused inputs and I/O pins be properly termi-
nated. Allowing unused inputs and I/O pins to float can
cause the voltage to be in the linear region of the CMOS
input structures, which can increase the power consump-
tion of the device. Xilinx recommends the use of 10K
pull-up resistors for the termination. Using pull-up resistors
allows the flexibility of using these pins should late design
changes require additional I/O. These unused pins may
also be tied directly to V
CC
, but this will make it more diffi-
cult to reclaim the use of the pin, should this be needed by
a subsequent design revision. See the application note
Ter-
minating Unused I/O Pins in Xilinx XPLA1 and XPLA2
CoolRunner CPLDs
for more information.
Figure 3: XCR3032 Macrocell Architecture
CT2
CT3
CT4
CT5
V
CC
GND
INIT
(P or R)
D/T
Q
SP00440
CLK0
PAL
PLA
CLK0
CLK1
CLK1
TO ZIA
GND
CT0
CT1
GND
GTS
xcr3032.fm Page 4 Monday, October 9, 2000 6:44 PM
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