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參數(shù)資料
| 型號： | XCF32PVOG48C |
| 廠商： | XILINX INC |
| 元件分類： | DRAM |
| 英文描述： | Platform Flash In-System Programmable Configuration PROMS |
| 中文描述： | 32M X 1 CONFIGURATION MEMORY, PDSO48 |
| 封裝： | LEAD-FREE, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 27/46頁 |
| 文件大?。?/td> | 525K |
| 代理商： | XCF32PVOG48C |
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Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
27
R
AC Electrical Characteristics
AC Characteristics Over Operating Conditions
XCFxxS and XCFxxP PROM as Configuration Slave with CLK Input Pin as Clock Source
Symbol
Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
Units
Min
Max
Min
Max
T
HCF
CF hold time to guarantee design revision selection is
sampled when V
CCO
= 3.3V or 2.5V
(9)
300
300
ns
CF hold time to guarantee design revision selection is
sampled when V
CCO
= 1.8V
(9)
300
300
ns
T
CF
CF to data delay when VCCO = 3.3V or 2.5V
(8)
–
–
–
25
ns
CF to data delay when VCCO = 1.8V
(8)
–
–
–
25
ns
T
OE
OE/RESET to data delay
(6)
when V
CCO
= 3.3V or 2.5V
–
10
–
25
ns
OE/RESET to data delay
(6)
when V
CCO
= 1.8V
–
30
–
25
ns
T
CE
CE to data delay
(5)
when V
CCO
= 3.3V or 2.5V
–
15
–
25
ns
CE to data delay
(5)
when V
CCO
= 1.8V
–
30
–
25
ns
T
CAC
CLK to data delay
(7)
when V
CCO
= 3.3V or 2.5V
–
15
–
25
ns
CLK to data delay
(7)
when V
CCO
= 1.8V
–
30
–
25
ns
T
OH
Data hold from CE, OE/RESET, CLK, or
CF
when V
CCO
= 3.3V or 2.5V
(8)
0
–
5
–
ns
Data hold from CE, OE/RESET, CLK, or
CF
when V
CCO
= 1.8V
(8)
0
–
5
–
ns
CE
OE/RE
S
ET
CLK
BU
S
Y
(option
a
l)
DATA
T
CE
T
LC
T
HC
T
S
CE
T
OE
T
CAC
T
HCE
T
HOE
T
CYC
T
OH
T
DF
T
OH
T
HB
T
S
B
CF
EN_EXT_
S
EL
REV_
S
EL[1:0]
T
S
XT
T
HXT
T
S
RV
T
HRV
d
s
12
3
_22_122905
T
S
XT
T
HXT
T
S
RV
T
HRV
T
CF
T
HCF
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|---|---|
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| XCF3-81 | 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XCF3-81 |
| XCF3-81-J1 | 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XCF3-81-J1 |
| XCF3-81-J1Z1 | 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XCF3-81-J1Z1 |
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