參數(shù)資料
型號： XCF32PFSG48C
廠商： Xilinx Inc
文件頁數(shù)： 27/35頁
文件大?。?/td> 0K
描述： IC PROM SRL 1.8V 32M 48CSBGA
產(chǎn)品變化通告： Package Assemble Change 01/Jan/2007
標準包裝： 108
可編程類型： 系統(tǒng)內(nèi)可編程
存儲容量： 32Mb
電源電壓： 1.65 V ~ 2 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-BFBGA，CSPBGA
供應商設備封裝： 48-CSP（8x9）
包裝： 托盤
產(chǎn)品目錄頁面： 601 (CN2011-ZH PDF)
其它名稱： 122-1457
Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
33
R
07/20/04
2.4
Added Pb-free package options VOG20, FSG48, and VOG48.
Figure 6, page 16, and Figure 7, page 17: Corrected connection name for FPGA DOUT
(OPTIONAL Daisy-chained Slave FPGAs with different configurations) from DOUT to DIN.
Section "Absolute Maximum Ratings," page 13: Removed parameter TSOL from table. (TSOL
information can be found in Package User Guide.)
Table 2, page 3: Removed reference to XC2VP125 FPGA.
10/18/04
2.5
Table 1, page 1: Broke out VCCO / VCCJ into two separate columns.
Table 9, page 9: Added clarification of ID code die revision bits.
Table 10, page 10: Deleted TCKMIN2 (bypass mode) and renamed TCKMIN1 to TCKMIN.
Table "Recommended Operating Conditions," page 14: Separated VCCO and VCCJ parameters.
Added most parameter values for XCF08P, XCF16P, XCF32P devices.
Added Footnote (1) to ICCO specifying no-load conditions.
Added most parameter values for XCF08P, XCF16P, XCF32P devices.
Expanded Footnote (1) to include XCF08P, XCF16P, XCF32P devices.
Added Footnote (8) through (11) relating to CLKOUT conditions for various parameters.
Added rows to TCYC specifying parameters for parallel mode.
Added rows specifying parameters with decompression for TCLKO, TCOH, TFF, TSF.
Added TDDC (setup time with decompression).
Added most parameter values for XCF08P, XCF16P, XCF32P devices.
Separated Footnote (5) into Footnotes (5) and (6) to specify different derivations of TCYC,
depending on whether dual-purpose configuration pins persist as configuration pins, or
become general I/O pins after configuration.
03/14/05
2.6
Added Virtex-4 LX/FX/SX configuration data to Table 2.
Corrected Virtex-II configuration data in Table 2.
Corrected Virtex-II Pro configuration data in Table 2.
Added Spartan-3L configuration data to Table 2.
Added Spartan-3E configuration data to Table 2.
Paragraph added to FPGA Master SelectMAP (Parallel) Mode (1).
Changes to DC Characteristics
TOER changed, Page 15.
IOL changed for VOL, Page 15.
VCCO added to test conditions for IIL, IILP, IIHP,and IIH, Page 15. Values modified for IILP and
IIHP.
Changes to AC Characteristics
TLC and THC modified for 1.8V, Page 19.
New rows added for TCEC and TOEC, Page 18.
Minor changes to grammar and punctuation.
Added explanation of "Preliminary" to DC and AC Electrical Characteristics.
07/11/05
2.7
Move from "Preliminary" to "Product Specification"
Corrections to Virtex-4 configuration bitstream values
Minor changes to Figure 7, page 17, Figure 12, page 22, Figure 13, page 23, and Figure 16,
page 31
Change to "Internal Oscillator," page 8 description
Change to "CLKOUT," page 8 description
12/29/05
2.8
Update to the first paragraph of "IEEE 1149.1 Boundary-Scan (JTAG)," page 5.
Added JTAG cautionary note to Page 5.
Corrected logic values for Erase/Program (ER/PROG) Status field, IR[4], listed under "XCFxxP
Date
Version
Revision
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